White Electronic Designs
CK
AVG
(MIN) is the smallest clock rate allowed, except a deviation due to allowed
clock jitter. Input clock jitter is allowed provided it does not exceed values specified.
Also, the jitter must be of a random Gaussian distribution in nature.
The inputs to the DRAM must be aligned to the associated clock; that is, the actual
clock that latches it in. However, the input timing (in ns) references to the
t
CK
AVG
when determining the required number of clocks. The following input parameters are
determined by taking the specified percentage times the tCKAVG rather thank
t
CK:
t
IPW,
t
DIPW,
t
DQSS,
t
DQSH,
t
DQSL,
t
DSS,
t
DH,
t
WPST, and
t
WPRE.
Spread spectrum is not included in the jitter specification values. However, the input
clock can accommodate spread spectrum at a sweep rate in the range 20–60 KHz
with additional one percent of
t
CK
AVG
as a long-term jitter component; however,
the spread spectrum may not use a clock rate below
t
CK
AVG
(MIN) or above
t
CK
AVG
(MAX).
The period jitter (
t
JIT
PER
) is the maximum deviation in the clock period from the
average or nominal clock allowed in either the positive or negative direction. JEDEC
specifies tighter jitter numbers during DLL locking time. During DLL lock time, the
jitter values should be 20 percent less than noted in the table (DLL locked).
The half-period jitter (
t
JIT
DTY
) applies to either the high pulse of clock or the low
pulse of clock; however, the two cumulatively can not exceed
t
JIT
PER
.
The cycle-to-cycle jitter (
t
JIT
CC
) is the amount the clock period can deviate from
one cycle to the following cycle. JEDEC specifies tighter jitter numbers during DLL
locking time. During DLL lock time, the jitter values should be 20 percent less than
noted in the table (DLL locked).
The cumulative jitter error (
t
ERR
nPER
) where n is 2, 3, 4, 5, 6–10, or 11–50, is the
amount of clock time allowed to consecutively accumulate away from the average
clock over any number of clock cycles.
The DRAM output timing is aligned to the nominal or average clock. Most output
t
W3HG128M64EEU-D4
ADVANCED*
37.
38.
44.
39.
45.
40.
41.
46.
47.
42.
48.
49.
43.
parameters must be derated by the actual jitter error when input clock jitter is
present; this will result in each parameter becoming larger. The following parameters
are required to be derated by subtracting
t
ERR
5PER
(MAX):
t
AC(MIN),
t
DQSCK(MIN),
t
HZ(MIN),
t
LZ
DQ
(MIN),
t
AON(MIN); while these following parameters are required
to be derated by subtracting
t
ERR
5PER
(MIN):
t
AC(MAX),
t
DQSCK(MAX),
t
HZ(MAX),
t
LZ
DQ
(MAX),
t
AON(MAX). The parameter
t
RPRE(MIN) is derated by subtracting
t
JITPER(MAX), while
t
PRPE(MAX), is derated by subtracting
t
JIT
PER
(MAX) . The
parameter
t
RPST(MAX), is dated by subtracting
t
JIT
DTY
(MIN).
Half-clock output parameters must be derated by the actual
t
ERR
5PER
and
t
JIT
DTY
when input clock jitter is present; this will result in each parameter becoming
larger. The parameter
t
AOF(MIN) is required to be derated by subtracting both
t
ERR
5PER
(MAX) and
t
JIT
PER
(MAX). The parameter
t
AOF(MAX) is required to be
derated by subtracting both
t
ERR
5PER
(MIN) and
t
JIT
DTY
(MIN).
MIN(
t
CL,
t
CH) refers to the smaller of the actual clock LOW time and the actual
clock HIGH time driven to the device. The clock's half period must also be of a
Gaussian distribution;
t
CH
AVG
and
t
CL
AVG
must be met with or with our clock jitter
and with or without duty cycle jitter.
t
CH
AVG
and
t
CL
AVG
are the average of any 200
consecutive CK falling edges.
t
HP (MIN) is the lesser of
t
CL and
t
CH actually applied to the device CK and CK#
inputs; thus,
t
HP(MIN) ≥ the lesser of
t
CL
ABS
(MIN) and
t
CH
ABS
(MIN).
t
QH =
t
HP -
t
QHS; the worst case
t
QH would be the smaller of
t
CL
ABS
(MAX) or
t
CH
ABS
(MAX) times
t
CK
ABS
(MIN) -
t
QHS. Minimizing the amount of
t
CH
AVG
offset and
value of
t
JIT
DTY
will provide a larger
t
QH, which in turn will provide a larger valid data
out window.
JEDEC specifies using
t
ERR
6-10PER
when derating clock-related output timing (notes
43–44). Micron requires less derating by allowing
t
ERR
5PER
to be used.
Requires 8
t
CK for backward compatibility.
March 2006
Rev. 0
11
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
