White Electronic Designs
AC CHARACTERISTICS
Parameter
Clock Time
Clock Access Time
Output enable to Data Valid
Clock High to Output Low-Z
Output Hold from Clock High
Output Enable Low to output Low-Z
Output Enable High to Output High-Z
Clock High to Output High-Z
Clock High Pulse Width
Clock Low Pulse Width
Address Setup to Clock High
CKE Setup to Clock High
Data Setup to Clock High
Write Setup to Clock High
Address Advance to Clock High
Chip Select Setup to Clock High
Address Hold to Clock high
CKE Hold to Clock High
Data Hold to Clock High
Write Hold to Clock High
Address Advance to Clock High
Chip Select Hold to Clock High
ZZ High to Power Down
ZZ Low to Power Up
Symbol
t
CYC
t
CD
t
OE
t
LZC
t
OH
t
LZOE
t
HZOE
t
HZC
t
CH
t
CL
t
AS
t
CES
t
DS
t
WS
t
ADVS
t
CSS
t
AH
t
CEH
t
DH
t
WH
t
ADVH
t
CSH
t
PDS
t
PUS
250MHz
Min
4.0
--
--
1.5
1.5
0.0
--
--
1.7
1.7
1.2
1.2
1.2
1.2
1.2
1.2
0.3
0.3
0.3
0.3
0.3
0.3
2
2
2.6
2.6
--
--
--
2.6
2.6
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
225MHz
Min
4.4
--
--
1.5
1.5
0.0
--
--
2.0
2.0
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
2
2
2.8
2.8
--
--
--
2.8
2.8
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
200MHz
Min
5.0
--
--
1.5
1.5
0.0
--
--
2.0
2.0
1.4
1.4
1.4
1.4
1.4
1.4
0.4
0.4
0.4
0.4
0.4
0.4
2
2
3.0
3.0
--
--
--
3.0
3.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
166MHz
Min
6.0
--
--
1.5
1.5
0.0
--
--
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
2
3.5
3.5
--
--
--
3.0
3.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
WED2ZL361MS
150MHz
Min
6.7
--
--
1.5
1.5
0.0
--
--
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
2
3.8
3.8
--
--
--
3.0
3.0
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
133MHz
Min
7.5
--
--
1.5
1.5
0.0
--
--
2.2
2.2
1.5
1.5
1.5
1.5
1.5
1.5
0.5
0.5
0.5
0.5
0.5
0.5
2
2
4.2
4.2
--
--
--
3.5
3.5
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
--
Max
Units
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
cycle
cycle
NOTES:
1. All Address inputs must meet the specified setup and hold times for all rising clock (CK) edges when ADV is sampled low and CEx# is sampled valid. All other
synchronous inputs must meet the specified setup and hold times whenever this device is chip selected.
2. Chip enable must be valid at each rising edge of CK (when ADV is Low) to remain enabled.
3. A write cycle is defined by WE# low having been registered into the device at ADV Low. A Read cycle is defined by WE# High with ADV Low. Both cases must
meet setup and hold times.
(0 ≤ T
A
≤ 70°C, V
CC
= 2.5V ± 5%; Commercial or -40°C ≤ Ta ≤ 85°C; V
CC
= 2.5V ± 5%; Industrial)
Parameter
Input Pulse Level
Input Rise and Fall Time (Measured at 20% to 80%)
Input and Output Timing Reference Levels
Output Load
Value
0 to 2.5V
1.0V/ns
1.25V
See Output Load (A)
AC TEST CONDITIONS
OUTPUT LOAD (A)
Dout
Zo=50Ω
RL=50Ω
VL=1.25V
30pF*
OUTPUT LOAD (B)
(for t
LZC
, t
LZOE
, t
HZOE
, and t
HZC
)
+2.5V
Dout
1538Ω
1667Ω
5pF*
*Including Scope and Jig Capacitance
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
Oct, 2002
Rev. 5
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
