White Electronic Designs
POWER CONSUMTION
WED3C755E8M-XBX
V
CC
=AV
CC
=2.0±0.1V, OV
CC
=3.3V ±5% V
DC
, GND=0 V
DC
, 0≤Tj<105°C
Processor (CPU) Frequency/L2 Fre-
quency
300/150 MHz
Full-on Mode
Doze Mode
Nap Mode
Sleep Mode
Typical
Maximum
Maximum
Maximum
Maximum
3.
4.1
6.7
2.5
1700
1200
350/175MHz
4.6
7.9
2.8
1800
1300
W
W
W
mW
mW
1, 3
1, 2
1, 2
1, 2
1, 2
Unit
Notes
Sleep Mode–PLL and DLL Disabled
Maximum
NOTES:
1.
These values apply for all valid 60x bus and L2 bus ratios. The values do
not include OV
CC
; AV
CC
and L2AV
CC
suppling power. OV
CC
power is system
dependent, but is typically <10% of V
CC
power. Worst case power consumption,
for AV
CC
=15mW and L2AV
CC
=15mW.
2.
Maximum power is measured at V
CC
=2.1V while running an entirely cache-
resident, contrived sequence of instructions which keep the execution units
maximally busy.
500
500
mW
1, 2
Typical power is an average value measured at V
CC
=AV
CC
=L2AV
CC
=2.0V,
OV
CC
=L2OV
CC
=3.3V in a system, executing typical applications and benchmark
sequences.
BGA THERMAL RESISTANCE
Description
Junction to Ambient (No Airflow)
Junction to Ball
Junction to Case (Top)
Symbol
Theta JA
Theta JB
Theta JC
PPC
14.2
8.6
0.1
SSRAM
11.2
5.7
0.1
Units
C/W
C/W
C/W
Notes
1
1
1
NOTE 1: Refer to PBGA Thermal Resistance Correlation at www.whiteedc.com in the application notes section for modeling conditions
L2 CACHE CONTROL REGISTER (L2CR)
The L2 cache control register, shown in Figure 5, is a supervisor-level, implementation-specific SPR used to configure
and operate the L2 cache. It is cleared by hard reset or power-on reset.
FIG. 5 - L2 CACHE CONTROL REGISTER (L2CR)
L2E
L2PE
L2SIZ
L2CLK
L2RAM
L2DO
L2I
L2CTL L2WT L2TS
L20H
L2SL
L2DF
L2BYP
0
0
L2IO
L2CS
L2DRO
L2CTR
L2IP
0
1 2
3 4
6 7
8
9
10 11 12 13 14 15 16 17 18 19 20 21
22 23 24
30 31
The L2CR bits are described in Table 1.
Reserved
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
May, 2003
Rev 2
8
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com