White Electronic Designs
WED3DL3216V
SINGLE BIT READ-WRITE CYCLE (SAME PAGE) @CAS LATENCY=3, BURST LENGTH=1
0
CLOCK
t
CC
CKE
t
CH
t
CL
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
HIGH
t
RCD
t
RAS
CE#
t
RCD
t
SS
RAS#
t
SS
CAS#
t
SS
ADDR
Ra
t
SH
Ca
t
SS
Cb
t
SH
Cc
Rb
t
SH
t
CCD
t
SH
t
SS
t
SH
t
RP
Note 2
Note 2,3
Note 2,3
Note 2,3
Note 4
Note 2
BA
BS
BS
BS
BS
BS
BS
A10/AP
Ra
Note 3
Note 3
Note 3
Note 4
Rb
t
RAC
t
SAC
DQ
t
SLZ
Qa
t
SS
Db
t
SH
Qc
t
OH
t
SS
t
SH
WE#
t
SS
DQM
t
SH
Row Active
Read
Write
Read
Precharge
Row Active
DONT’ CARE
NOTES:
1.
All input except CKE & DQM can be don’t care when CE is high at the CK high
going edge.
2.
Bank active & read/write are controlled by BA
0
~BA
1.
BA0
0
0
1
1
BA1
0
1
0
1
Active & Read/Write
Bank A
Bank B
Bank C
Bank D
3.
Enable and disable auto precharge function are controlled by A10/AP in
read/write command.
A10/AP
BA
0
0
0
0
1
1
0
1
0
1
1
BA
1
0
1
0
1
0
1
0
1
Operation
Disable auto precharge, leave bank A active at end of burst.
Disable auto precharge, leave bank B active at end of burst.
Disable auto precharge, leave bank C active at end of burst.
Disable auto precharge, leave bank D active at end of burst.
Enable auto precharge, precharge bank A at end of burst.
Enable auto precharge, precharge bank B at end of burst.
Enable auto precharge, precharge bank C at end of burst.
Enable auto precharge, precharge bank D at end of burst.
4.
A10/AP and BA0~BA1 control bank precharge when precharge command is
asserted.
A10/AP
0
0
0
0
1
BA0
0
0
1
1
x
BA1
0
1
0
1
x
Precharge
Bank A
Bank B
Bank C
Bank D
All Banks
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
12
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
