WED3DL3216V
White Electronic Designs
PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
3
5
6
18
19
2
4
7
8
9
11
12
13
15
16
17
0
1
10
14
CLOCK
CKE
HIGH
CE#
tRCD
RAS#
Note 2
CAS#
ADDR
Rb
Cb0
Ra
Cb0
Ca0
BA
A10/AP
CL = 2
Ra
tRDL
Qa0
Qa1
Qb0
Qa1
Qb1
Qb0
Qb2
Dd1
Dc0
Dc0
Dc1
Dd0
Dd0
DQ
tCDL
CL = 3
Qa0
Qb1
Dc1
Dd1
WE#
Precharge
(All Banks)
Note 1
Note 3
DQM
Precharge
(A-Bank)
Write
(A-Bank)
Read
(A-Bank)
Read
(A-Bank)
Row Active
(A-Bank)
Write
(A-Bank)
DON’T CARE
NOTES:
1.
2.
3.
To write data before burst read ends, DQM should be asserted three cycles prior to write command to avoid bus contention.
Row precharge will interrupt writing. Last data input, tRDL before Row precharge, will be written.
DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked
internally.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
15
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
