WED3DL3216V
White Electronic Designs
PAGE WRITE CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
3
5
6
18
19
2
4
7
8
9
11
12
13
15
16
17
0
1
10
14
CLOCK
CKE
HIGH
CE#
RAS#
Note 2
CAS#
ADDR
RBb
CAa
CBb
CAc
CBd
RAa
BA
A10/AP
DQ
RAa
RBb
tCDL
DAa1 DAa2 DAa3
tRDL
DBd1
DAa0
DBb0
DBb1
DBb2
DBb3
DAc0 DAc1 DBd0
WE#
Note 1
DQM
Precharge
(All Banks)
Row Active
(B-Bank)
Write
(B-Bank)
Write
(A-Bank)
Write
(B-Bank)
Precharge
(Both Banks)
Row Active
(A-Bank)
Write
(A-Bank)
DON’T CARE
NOTES:
1.
2.
To interrupt burst write by Row precharge, DQM should be asserted to mask invalid input data.
To interrupt burst write by Row precharge, both the write and the precharge banks must be the same.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
January, 2004
Rev. 0
17
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
