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WED7P032ATA8003C25 参数 Datasheet PDF下载

WED7P032ATA8003C25图片预览
型号: WED7P032ATA8003C25
PDF下载: 下载PDF文件 查看货源
内容描述: 32MB到4GB闪存卡 [32MB to 4GB Flash Card]
分类和应用: 闪存
文件页数/大小: 10 页 / 222 K
品牌: WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
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White Electronic Designs
AC CHARACTERISTICS:
WED7PxxxATA80xxC25
Attribute Memory Read Timing Specification
Attribute Memory access time is defined as 300ns. Detailed timing specs are shown in Table below.
Speed Version
Item
Read Cycle Time
Address Access Time
Card Enable Access Time
Output Enable Access Time
Output Disable Time from CE
Output Disable Time from OE
Address Setup Time
Output Enable Time from CE
Output Enable Time from OE
Data Valid from Address Change
Symbol
tc(R)
ta(A)
ta(CE)
ta(OE)
tdis(CE)
tdis(OE)
tsu(A)
ten(CE)
ten(OE)
tv(A)
IEEE Symbol
t
AVAV
t
AVQV
t
ELQV
t
GLQV
t
EHQZ
t
GHQZ
t
AVGL
t
ELQNZ
t
GLQNZ
t
AXQX
Min ns.
300
300 ns
Max ns.
300
300
150
100
100
30
5
5
0
Note: All times are in nanoseconds. The CE# signal or both the OE# signal and the WE# signal must be de-asserted between consecutive cycle operations.
Configuration Register (Attribute Memory) Write Timing Specification
The Card Configuration write access time is defined as 250ns. Detailed timing specifications are shown in Table below.
Speed Version
Item
Write Cycle Time
Write Pulse Width
Address Setup Time
Write Recovery Time
Data Setup Time for WE
Data Hold Time
Note: All times are in nanoseconds.
250 ns
Symbol
tc(W)
tw(WE)
tsu(A)
trec(WE)
tsu(D-WEH)
th(D)
IEEE Symbol
t
AVAV
t
WLWH
t
AVWL
t
WMAX
t
DVWH
t
WMDX
Min ns
250
150
30
30
80
30
Max ns
Common Memory Read Timing Specification
Item
Output Enable Access Time
Output Disable Time from OE
Address Setup Time
Address Hold Time
CE Setup before OE
CE Hold following OE
Wait Delay Falling from OE
Data Setup for Wait Release
Wait Width Time
Symbol
ta(OE)
tdis(OE)
tsu(A)
th(A)
tsu(CE)
th(CE)
tv(WT-OE)
tv(WT)
tw(WT)
IEEE Symbol
t
GLQV
t
GHQZ
t
AVGL
t
GHAX
t
ELGL
t
GHEH
t
GLWTV
t
QVWTH
t
WTLWTH
Min ns.
Max ns.
125
100
30
20
0
20
35
0
350 (3000 for CF+)
Note: The maximum load on -WAIT# is 1 LSTTL with 50pF total load. All times are in nanoseconds. The WAIT# signal may be ignored if the OE# cycle to cycle time is greater than
the Wait Width time. The Max Wait Width time can be determined from the Card Information Structure. The Wait Width time meets the PCMCIA specification of 12ps but is
intentionally less in this specification.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
5
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com