White Electronic Designs
AC CHARACTERISTICS (cont'd):
WED7PxxxATA80xxC25
I/O Input (Read) Timing Specification
Item
Data Delay after IORD
Data Hold following IORD
IORD Width Time
Address Setup before IORD
Address Hold following IORD
CE Setup before IORD
CE Hold following IORD
REG Setup before IORD
REG Hold following IORD
INPACK Delay Falling from IORD
INPACK Delay Rising from IORD
IOIS16 Delay Falling from Address
IOIS16 Delay Rising from Address
Wait Delay Falling from IORD
Data Delay from Wait Rising
Wait Width Time
Symbol
td(IORD)
th(IORD)
tw(IORD)
tsuA(IORD)
thA(IORD)
tsuCE(IORD)
thCE(IORD)
tsuREG(IORD)
thREG(IORD)
tdfINPACK(IORD)
tdrINPACK(IORD)
tdfIOIS16(ADR)
tdrIOIS16(ADR)
tdWT(IORD)
td(WT)
tw(WT)
IEEE Symbol
t
IGLQV
t
IGHQX
t
IGLIGH
t
AVIGL
t
IGHAX
t
ELIGL
t
IGHEH
t
RGLIGL
t
IGHRGH
t
IGLIAL
t
IGHIAH
t
AVISL
t
AVISH
t
IGLWTL
t
WTHQV
t
WTLWTH
Min ns.
0
165
70
20
5
20
5
0
0
Max ns.
100
45
45
35
35
35
0
350 (3000 for CF+)
Note: Maximum load on WAIT#, INPACK# and I0IS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT# high to IORD# high is Onsec, but
minimum IORD# width must still be met. Wait Width time meets PCMCIA specification of 12ps but is intentionally less in this spec.
I/O Output (Write) Timing Specification
Item
Data Setup before IOWR
Data Hold following IOWR
IOWR Width Time
Address Setup before IOWR
Address Hold following IOWR
CE Setup before IOWR
CE Hold following IOWR
REG Setup before IOWR
REG Hold following IOWR
IOIS16 Delay Falling from Address
IOIS16 Delay Rising from Address
Wait Delay Falling from IOWR
IOWR high from Wait high
Wait Width Time
Symbol
tsu(IOWR)
th(IOWR)
tw(IOWR)
tsuA(IOWR)
thA(IOWR)
tsuCE(IOWR)
thCE(IOWR)
tsuREG(IOWR)
thREG(IOWR)
tdfIOIS16(ADR)
tdrIOIS16(ADR)
tdWT(IOWR)
tdrIOWR(WT)
tw(WT)
IEEE Symbol
t
DVIWH
t
IWHDX
t
IWLIWH
t
AVIWL
t
IWHAX
t
ELIWL
t
IWHEH
t
RGLIWL
t
IWHRGH
t
AVISL
t
AVISH
t
IWLWTL
t
WTJIWH
t
WTLWTH
Min ns.
60
30
165
70
20
5
20
5
0
Max ns.
35
35
35
0
350 (3000for CF+)
Note: The maximum load on WAIT#, INPACK#, and I0IS16# is 1 LSTTL with 50pF total load. All times are in nanoseconds. Minimum time from WAIT# high to IOWR# high is Onsec,
but minimum IOWR# width must still be met. The Wait Width time meets the PCMCIA specification of 12ps but is intentionally less in this specification.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July 2005
Rev. 1
6
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
