WED9LAPC2C16V8BC
White Electronic Designs
FIG. 7 SDRAM PAGE READ & WRITE CYCLE AT SAME BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
GCK
t
RCD
VCRAS#
VCCAS#
VCADDR
Note 2
Ca0
Cb0
Cd0
Cc0
Ra
VCBS
VCADDR9/AP
Ra
t
RDL
CL = 2
Qa0
Qa1
Qb2
Qb1
Qb2
Dc0
Dc1
Dd0
Dd1
VCDATA
t
CDL
CL = 3
Qa0
Qa1
Qb0
Qb1
Dc0
Dc1
Dd0
Dd1
VCWE#
Note 1
Note 3
VCDQM#
Read
(A-Bank)
Row Active
(A-Bank)
Read
(A-Bank)
Write
Precharge
(A-Bank)
Write
(A-Bank)
(A-Bank)
DON’T CARE
Notes:
1.
2.
3.
To write data before burst read ends. VCDQM# should be asserted three cycle prior to write command to avoid bus contention.
Row precharge will interrupt writing. Last data input, tRDL before Row precharge will be written.
VCDQM# should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be
masked internally.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July, 2000
Rev. 0
14
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
