WED9LAPC2C16V8BC
White Electronic Designs
FIG. 8 SDRAM PAGE READ CYCLE AT DIFFERENT BANK @ BURST LENGTH = 4
0
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
GCK
VCRAS#
VCCAS#
VCADDR
Note 1
CAa
RBb
CBb
CAc
CBd
CAe
RAa
VCBS
RAa
VCADDR9/AP
RBb
CL = 2
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2
QBb3
QAc0
QAc1
QBd0
QBd1
QAe0
QAe1
VCDATA
CL = 3
QAa0
QAa1
QAa2
QAa3
QBb0
QBb1
QBb2
QBb3
QAc0
QAc1
QBd0
QBd1
QAe0
QAe1
VCWE#
VCDQM#
Row Active
(A-Bank)
Row Active
(B-Bank)
Read
Read
Precharge
(A-Bank)
Read
Read
(A-Bank)
(A-Bank)
(B-Bank)
(B-Bank)
Read
(A-Bank)
DON’T CARE
Note:
1.
To interrupt a burst read by Row precharge, both the read and the precharge banks must be the same.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
July, 2000
Rev. 0
15
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
