White Electronic Designs
Output Functional Descriptions
Symbol
SSCK#
SSADS#
SSOE#
SSWE#
SSCE#
SDCK#
SDCE
SDRAS#
SDCAS#
SDWE#
Type
Input
Input
Input
Input
Input
Input
Signal
Pulse
Pulse
Pulse
Pulse
Pulse
Pulse
Polarity
Positive Edge
Active Low
Active Low
Positive Edge
Active Low
Active Low
Function
WED9LC6816V
The system clock input. All of the SSRAM inputs are sampled on the rising edge of the clock.
When sampled at the positive rising edge of the clock, SSADS#, SSOE#, and SSWE# define
the operation to be executed by the SSRAM.
SSCE# disable or enable SSRAM device operation.
The system clock input. All of the SDRAM inputs are sampled on the rising edge of the clock.
SDCE disable or enable device operation by masking or enabling all inputs except SDCK# and BWE
0-3
.
When sampled at the positive rising edge of the clock, SDCAS#, SDRAS#, and SDWE#
define the operation to be executed by the SDRAM.
Address bus for SSRAM and SDRAM
A
0
and A
1
are the burst address inputs for the SSRAM
During a Bank Active command cycle, A
0-11
, SDA
10
defines the row address (RA
0-10
) when
sampled at the rising clock edge.
A0-17
SDA10
Input
Level
—
During a Read or Write command cycle, A
0-7
defines the column address (CA
0-7
) when
sampled at the rising clock edge. In addition to the row address, SDA10 is used to invoke
Autoprecharge operation at the end of the Burst Read or Write Cycle. If SDA
10
is high,
autoprecharge is selected and A
12
and A
13
define the bank to be precharged. If SDA
10
is low,
autoprecharge is disabled.
During a Precharge command cycle, SDA
10
is used in conjunction with A
12
and A
13
to control
which bank(s) to precharge. If SDA
10
is high, all banks will be precharged regardless of
the state of A
12
and A
13
. If SDA
10
is low, then A
12
and A
13
are used to define which bank to
precharge.
DQ
0-31
BWE
0-3
V
CC
, V
SS
V
CCQ
Input
Output
Input
Supply
,
Supply
Level
Pulse
—
Data Input/Output are multiplexed on the same pins.
BWE
0-3
perform the byte write enable function for the SSRAM and DQM function for the SDRAM BWE
0
is
associated with DQ
0-7
, BWE
1
with DQ
8-15
, BWE
2
with DQ
16-23
and BWE
3
with DQ
24-31
.
Power and ground for the input buffers and the core logic.
Data base power supply pins, 3.3V (2.5V future).
Contact factory for ordering information.
White Electronic Designs Corp. reserves the right to change products or specifications without notice.
September, 2003
Rev. 1
3
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
