White Electronic Designs
WEDPN16M64VR-XB2X
16Mx64 REGISTERED SYNCHRONOUS DRAM
FEATURES
Registered for enhanced performace of bus speeds
• 100, 125, 133MHz
Package:
• 219 Plastic Ball Grid Array (PBGA), 25 x 25mm
Single 3.3V ±0.3V power supply
Fully Synchronous; all signals registered on positive
edge of system clock cycle
Internal pipelined operation; column address can be
changed every clock cycle
Internal banks for hiding row access/precharge
Programmable Burst length 1,2,4,8 or full page
8,192 refresh cycles
Commercial, Industrial and Military Temperature
Ranges
Organized as 16M x 64
• User configureable as 2 x 16M x 32
Weight: WEDPN16M64VR-XB2X - 2.5 grams
typical
GENERAL DESCRIPTION
The 128MByte (1Gb) SDRAM is a high-speed CMOS,
dynamic random-access, memory using 4 chips containing
268,435,456 bits. Each chip is internally configured as a
quad-bank DRAM with a synchronous interface. Each of
the chip’s 67,108,864-bit banks is organized as 8,192 rows
by 512 columns by 16 bits. The MCP also incorporates
two 16-bit universal bus drivers for input control signals
and addresses.
Read and write accesses to the SDRAM are burst oriented;
accesses start at a selected location and continue for
a programmed number of locations in a programmed
sequence. Accesses begin with the registration of an
ACTIVE command, which is then followed by a READ or
WRITE command. The address bits registered coincident
with the ACTIVE command are used to select the bank
and row to be accessed (BA0, BA1 select the bank; A0-
12 select the row). The address bits registered coincident
with the READ or WRITE command are used to select the
starting column location for the burst access.
The SDRAM provides for programmable READ or WRITE
burst lengths of 1, 2, 4 or 8 locations, or the full page, with
a burst terminate option. An AUTO PRECHARGE function
may be enabled to provide a self-timed row precharge that
is initiated at the end of the burst sequence.
The 1Gb SDRAM uses an internal pipelined architecture
to achieve high-speed operation. This architecture is
compatible with the 2n rule of prefetch architectures, but
it also allows the column address to be changed on every
clock cycle to achieve a high-speed, fully random access.
Precharging one bank while accessing one of the other
three banks will hide the precharge cycles and provide
seamless, high-speed, random-access operation.
The 1Gb SDRAM is designed to operate in 3.3V, low-power
memory systems. An auto refresh mode is provided, along
with a power-saving, power-down mode.
All inputs and outputs are LVTTL compatible. SDRAMs offer
substantial advances in DRAM operating performance,
including the ability to synchronously burst data at a high
data rate with automatic column-address generation,
the ability to interleave between internal banks in order
to hide precharge time and the capability to randomly
change column addresses on each clock cycle during a
burst access.
BENEFITS
51% SPACE SAVINGS
17% I/O Reduction
Reduced part count
Reduced trace lengths for lower parasitic
capacitance
Glue-less connection to memory controller/PCI
Bridge
Suitable for hi-reliability applications
* This product is subject to change without notice.
January 2005
Rev. 0
1
White Electronic Designs Corporation • (602) 437-1520 • www.wedc.com
WEDC [ WHITE ELECTRONIC DESIGNS CORPORATION ]
