欢迎访问ic37.com |
会员登录 免费注册
发布采购

WCFS4016V1C-TC12 参数 Datasheet PDF下载

WCFS4016V1C-TC12图片预览
型号: WCFS4016V1C-TC12
PDF下载: 下载PDF文件 查看货源
内容描述: 256K ×16静态RAM [256K x 16 Static RAM]
分类和应用:
文件页数/大小: 9 页 / 217 K
品牌: WEIDA [ WEIDA SEMICONDUCTOR, INC. ]
 浏览型号WCFS4016V1C-TC12的Datasheet PDF文件第1页浏览型号WCFS4016V1C-TC12的Datasheet PDF文件第2页浏览型号WCFS4016V1C-TC12的Datasheet PDF文件第3页浏览型号WCFS4016V1C-TC12的Datasheet PDF文件第5页浏览型号WCFS4016V1C-TC12的Datasheet PDF文件第6页浏览型号WCFS4016V1C-TC12的Datasheet PDF文件第7页浏览型号WCFS4016V1C-TC12的Datasheet PDF文件第8页浏览型号WCFS4016V1C-TC12的Datasheet PDF文件第9页  
WCFS4016V1C
AC Switching Characteristics
Over the Operating Range
WCFS4016V1C 12ns
Parameter
READ CYCLE
t
power[4]
t
RC
t
AA
t
OHA
t
ACE
t
DOE
t
LZOE
t
HZOE
t
LZCE
t
HZCE
t
PU
t
PD
t
DBE
t
LZBE
t
HZBE
WRITE CYCLE
t
WC
t
SCE
t
AW
t
HA
t
SA
t
PWE
t
SD
t
HD
t
LZWE
t
HZWE
t
BW
Write Cycle Time
CE LOW to Write End
Address Set-Up to Write End
Address Hold from Write End
Address Set-Up to Write Start
WE Pulse Width
Data Set-Up to Write End
Data Hold from Write End
WE HIGH to Low Z
WE LOW to High Z
Byte Enable to End of Write
8
12
8
8
0
0
8
6
0
3
6
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
V
CC
(typical) to the first access
Read Cycle Time
Address to Data Valid
Data Hold from Address Change
CE LOW to Data Valid
OE LOW to Data Valid
OE LOW to Low Z
OE HIGH to High Z
CE LOW to Low Z
CE HIGH to High Z
CE LOW to Power-Up
CE HIGH to Power-Down
Byte Enable to Data Valid
Byte Enable to Low Z
Byte Disable to High Z
0
6
0
12
6
3
6
0
6
3
12
6
1
12
12
µs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Description
Min.
Max.
Unit
Notes:
3. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V.
4. t
POWER
gives the minimum amount of time that the power supply should be at typical Vcc values until the first memory access can be performed.
5. t
HZOE
, t
HZCE
, and t
HZWE
are specified with a load capacitance of 5pF as in part (a) of AC Test Loads. Transition is measured
±
500 mV from steady-state voltage.
6. At any given temperature and voltage condition, t
HZCE
is less than t
LZCE
, t
HZOE
is less than t
LZOE
, and t
HZWE
is less than t
LZWE
for any given device.
7. The internal write time of the memory is defined by the overlap of CE LOW, and WE LOW. CE and WE must be LOW to initiate a write, and the transition of either of
these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.
8. The minimum write cycle time for Write Cycle No. 3 (WE controlled, OE LOW) is the sum of t
HZWE
and t
SD
.
4