W28V400BT85C 参数 Datasheet PDF下载

W28V400B/T

The access time is 85ns (t

AVQV

) over the commercial temperature range (0° C to +70° C) and V

DD

supply voltage range of 4.75V to 5.25V. At lower V

DD

voltages, the access times are 90ns (4.5V to

5.5V), 100 nS (3.0V to 3.6V) and 120 nS (2.7V to 3.6V).

The Automatic Power Savings (APS) feature substantially reduces active current when the device is in

static mode (addresses not switching). In APS mode, the typical I

CCR

current is 1mA at V

DD

= 5V

.

When #CE and #RESET pins are at V

DD

, the I

CC

CMOS standby mode is enabled. When the #RESET

pin is at V

SS

, deep power-down mode is enabled which minimizes power consumption and provides

write protection during reset. A reset time (tPHQV) is required from #RESET switching high until

outputs are valid. Likewise, the device has a wake time (tPHEL) from #RESET-high until writes to the

CUI are recognized. With #RESET at V

SS

, the WSM is reset and the status register is cleared.

The device is available in 48-lead TSOP (Thin Small Outline Package, 1.2 mm thick). Pinout is shown

in Figure 2.

4. BLOCK DIAGRAM

DQ0 -DQ15

Output Buffer

Input Buffer

I/O Logic

Identifier

Register

Output

Multiplexer

Status

Register

Data

Register

Command

User

Interface

A-1

VDD

#BYTE

#CE

#WE

#OE

#RESET

#WP

Data

Comparator

Parameter Block 0

Parameter Block 1

Parameter Block 2

Parameter Block 3

Parameter Block 4

Parameter Block 5

A0-A17

Boot Block 0

Boot Block 1

Input

Buffer

Y

Decoder

Y-Gating

Main Block 0

Main Block 1

Write

State

Machine

Main Block 5

Main Block 6

RY/#BY

Program/Erase

Voltage Switch

VPP

Address

Latch

X

Decoder

32K-Word

(64K-Byte)

Main Blocks

x7

VDD

VSS

Address

Counter

Figure 1. Block Diagram

-5-

Publication Release Date: April 11, 2003

Revision A4