W39F010
6.3
Boot Block Operation
There are two alternatives to set the boot block. The 16K-byte in the top/bottom location of this device
can be locked as boot block, which can be used to store boot codes. It is located in the last 16K bytes
or first 16K bytes of the memory with the address range from 1C000(hex) to 1FFFF(hex) for top
location or 00000(hex) to 03FFF(hex) for bottom location.
See Command Codes for Boot Block Lockout Enable for the specific code. Once this feature is set the
data for the designated block cannot be erased or programmed (programming lockout), other memory
locations can be changed by the regular programming method.
In order to detect whether the boot block feature is set on the first/last 16K-byte block or not, users
can perform software command sequence: enter the product identification mode (see Command
Codes for Identification/Boot Block Lockout Detection for specific code), and then read from address
0002(hex) for first(bottom) location or 1FFF2(hex) for last(top) location. If the DQ0/DQ1 of output
data is "1," the 16Kbytes boot block programming lockout feature will be activated; if the DQ0/DQ1 of
output data is "0," the lockout feature will be inactivated and the block can be erased/programmed.
To return to normal operation, perform a three-byte command sequence (or an alternate single-byte
command) to exit the identification mode. For the specific code, see Command Codes for
Identification/Boot Block Lockout Detection.
6.3.1
Low V
DD
Inhibit
To avoid initiation of a write cycle during V
DD
power-up and power-down, the W39F010 locks out
when V
DD
< 2.0V (see DC Characteristics section for voltages). The write and read operations are
inhibited when V
DD
is less than 2.0V typical. The W39F010 ignores all write and read operations until
V
DD
> 2,0V. The user must ensure that the control pins are in the correct logic state when V
DD
> 2.0V
to prevent unintentional writes.
6.3.2
Write Pulse "Glitch" Protection
Noise pulses of less than 10 nS (typical) on #OE, #CE, or #WE will not initiate a write cycle.
6.3.3
Logical Inhibit
Writing is inhibited by holding any one of #OE = V
IL
, #CE = V
IH
, or #WE = V
IH
. To initiate a write cycle
#CE and #WE must be a logical zero while #OE is a logical one.
6.3.4
Power-up Write Inhibit
Power-up of the device with #WE = #CE = V
IL
and #OE = V
IH
will not accept commands on the rising
edge of #WE except 5mS delay (see the power up timing in AC Characteristics). The internal state
machine is automatically reset to the read mode on power-up.
6.4
Command Definitions
Device operations are selected by writing specific address and data sequences into the command
register. Writing incorrect address and data values or writing them in the improper sequence will reset
the device to the read mode. "Command Definitions" defines the valid register command sequences.
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