W39F010P-70Z 参数 Datasheet PDF下载

W39F010

6.4.1

Read Command

The device will automatically power-up in the read state. In this case, a command sequence is not

required to read data. Standard microprocessor read cycles will retrieve array data. This default value

ensures that no spurious alteration of the memory content occurs during the power transition.

The device will automatically returns to read state after completing an Embedded Program or

Embedded Erase algorithm.

Refer to the AC Read Characteristics and Waveforms for the specific timing parameters.

6.4.2

Auto-select Command

Flash memories are intended for use in applications where the local CPU can alter memory contents.

As such, manufacture and device codes must be accessible while the device resides in the target

system.

The device contains an auto-select command operation to supplement traditional PROM programming

methodology. The operation is initiated by writing the auto-select command sequence into the

command register. Following the command write, a read cycle from address XX00H retrieves the

manufacture code of DAH. A read cycle from address XX01H returns the device code (W39F010 =

A1).

To terminate the operation, it is necessary to write the auto-select exit command sequence into the

register.

6.4.3

Byte Program Command

The device is programmed on a byte-by-byte basis. Programming is a four-bus-cycle operation. The

program command sequence is initiated by writing two "unlock" write cycles, followed by the program

set-up command. The program address and data are written next, which in turn initiate the Embedded

program algorithm. Addresses are latched on the falling edge of #CE or #WE, whichever happens

later and the data is latched on the rising edge of #CE or #WE, whichever happens first. The rising

edge of #CE or #WE (whichever happens first) begins programming using the Embedded Program

Algorithm. Upon executing the algorithm, the system is not required to provide further controls or

timings. The device will automatically provide adequate internally generated program pulses and verify

the programmed cell margin.

The automatic programming operation is completed when the data on DQ7 (also used as Data

Polling) is equivalent to the data written to this bit at which time the device returns to the read mode

and addresses are no longer latched (see "Hardware Sequence Flags"). Therefore, the device

requires that a valid address to the device be supplied by the system at this particular instance of time

for Data Polling operations. Data Polling must be performed at the memory location which is being

programmed.

Any commands written to the chip during the Embedded Program Algorithm will be ignored. If a

hardware reset occurs during the programming operation, the data at that particular location will be

corrupted.

Programming is allowed in any sequence and across page boundaries. Beware that a data "0" cannot

be programmed back to a "1". Attempting to program 0 back to 1, the toggle bit will stop toggling. Only

erase operations can convert "0"s to "1"s.

Refer to the Programming Command Flow Chart using typical command strings and bus operations.

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Publication Release Date: December 26, 2005

Revision A4