W681360
BCLKT
(BCLKR)
FST (FSR)
SHORT O R
LONG FRAM E
SYNC
PCMT
PCMR don't care
1
1
2
2
3
3
4
4
5
5
6
6
7
7
8
8
9
9
10
10
11
11
12 13
12
13
14
15
16 don't care
don't care
Receive Gain Adjust (BCLKR=1)
Transm it and Receive both use BCLKT. FST m ay occur at a different tim e than FSR.
Bits 14, 15, and 16, clocked into PCMR, are used for attenuation control for the
receive analog output.
FIGURE 7.7: RECEIVE GAIN ADJUST TIMING MODE
7.4.4. System Timing
The system can work at 256kHz, 512kHz, 1536kHz, 1544kHz, 2048kHz, 2560kHz, 4096kHz &
4800kHz master clock rates. The system clock is supplied through the master clock input MCLK and
can be derived from the bit-clock if desired. An internal pre-scaler is used to generate a fixed 256kHz
and 8kHz sample clock for the internal CODEC. The pre-scaler measures the master clock frequency
versus the Frame Sync frequency and sets the division ratio accordingly. If both Frame Syncs are
LOW for the entire frame sync period while the MCLK and BCLK pin clock signals are still present, the
W681360 will enter the low power standby mode. Another way to power down is to set the PUI pin to
LOW. When the system needs to be powered up again, the PUI pin needs to be set to HIGH and the
transmit Frame Sync pulse needs to be present. It will take two transmit Frame Sync cycles before the
pin PCMT becomes low impedance.
7.5. O
N
-C
HIP
P
OWER
A
MPLIFIER
The on-chip power amplifier is typically used to drive an external loudspeaker. The inverting input to
the power amplifier is available at pin PAI. The non-inverting input is tied internally to V
AG.
The
inverting output PAO– is used to provide a feedback signal to the PAI pin to set the gain of the power
amplifier outputs (PAO+ and PAO-). These push–pull outputs are capable of driving a 300Ω load to
1.772 V
PEAK
.
Connecting PAI to V
DD
will power down the power driver amplifiers and the PAO+ and PAO– outputs
will be high impedance.
- 14 -
Publication Release Date: September 2005
Revision A.2
WINBOND [ WINBOND ]
