W681360
7.2.1. Receive Gain Adjust Mode
The W681360 can be put in the receive path adjust mode by applying a logic “1” to the BCLKR pin
while all other clocks are clocked normally. The device is then in a position to read 16-bits of data,
with three additional coefficient bits an addend to the 13-bit digital voice data. These three coefficients
are used to program a receive path attenuation, thereby allowing the receive signal to be attenuated
according to the values in the following table. If the feature is not used the default value is 0dB.
TABLE 7.2: ATTENUATION COEFFICIENT RELATIONSHIP IN RECEIVE GAIN ADJUST MODE
Coefficient
000
001
010
011
100
101
110
111
Attenuation (dB)
0
3
6
9
12
15
18
21
7.3. P
OWER
M
ANAGEMENT
7.3.1. Analog and Digital Supply
The power supply for the analog and digital parts of the W681360 must be 2.7V to 5.25V. This supply
voltage is connected to the V
DD
pin. The V
DD
pin needs to be decoupled to ground through a 0.1
μF
ceramic capacitor.
7.3.2. Analog Ground Reference Bypass
The system has an internal precision voltage reference which generates the V
DD
/2 mid-supply analog
ground voltage. This voltage needs to be decoupled to V
SS
at the V
REF
pin through a 0.1
μF
ceramic
capacitor.
7.3.3. Analog Ground Reference Voltage Output
The analog ground reference voltage is available for external reference at the V
AG
pin. This voltage
needs to be decoupled to V
SS
through a 0.01
μF
ceramic capacitor. The analog ground reference
voltage is generated from the voltage on the V
REF
pin and is also used for the internal signal
processing.
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Publication Release Date: September 2005
Revision A.2
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