W77C32/W77C032A
AC:
F0:
RS.1-0:
Auxiliary carry: Set when the previous operation resulted in a carry from the high order
nibble.
User flag 0: General purpose flag that can be set or cleared by the user.
Register bank select bits:
RS1
0
0
1
1
OV:
F1:
P:
RS0
0
1
0
1
Register bank
0
1
2
3
Address
00-07h
08-0Fh
10-17h
18-1Fh
Overflow flag: Set when a carry was generated from the seventh bit but not from the 8
th
bit as a result of the previous operation, or vice-versa.
User Flag 1: General purpose flag that can be set or cleared by the user by software
Parity flag: Set/cleared by hardware to indicate odd/even number of 1’s in the
accumulator.
Watchdog Control
Bit:
7
SMOD_1
Mnemonic: WDCON
6
POR
5
-
4
-
3
WDIF
2
WTRF
1
EWT
0
RWT
Address: D8h
SMOD_1:This bit doubles the Serial Port 1 baud rate in mode 1, 2, and 3 when set to 1.
POR:
Power-on reset flag. Hardware will set this flag on a power up condition. This flag can be read
or written by software. A write by software is the only way to clear this bit once it is set.
WDIF: Watchdog Timer Interrupt Flag. If the watchdog interrupt is enabled, hardware will set this bit
to indicate that the watchdog interrupt has occurred. If the interrupt is not enabled, then this bit
indicates that the time-out period has elapsed. This bit must be cleared by software.
WTRF: Watchdog Timer Reset Flag. Hardware will set this bit when the watchdog timer causes a
reset. Software can read it but must clear it manually. A power-fail reset will also clear the bit.
This bit helps software in determining the cause of a reset. If EWT = 0, the watchdog timer will
have no affect on this bit.
EWT: Enable Watchdog timer Reset. Setting this bit will enable the Watchdog timer Reset function.
RWT: Reset Watchdog Timer. This bit helps in putting the watchdog timer into a know state. It also
helps in resetting the watchdog timer before a time-out occurs. Failing to set the RWT before
time-out will cause an interrupt, if EWDI (EIE.4) is set, and 512 clocks after that a watchdog
timer reset will be generated if EWT is set. This bit is self-clearing by hardware.
The WDCON SFR is set to a 0x0x0xx0b on an external reset. WTRF is set to a 1 on a Watchdog timer
reset, but to a 0 on power on/down resets. WTRF is not altered by an external reset. POR is set to 1
by a power-on reset. EWT is set to 0 on a Power-on reset and unaffected by other resets.
All the bits in this SFR have unrestricted read access. POR, EWT, WDIF and RWT require Timed
Access procedure to write. The remaining bits have unrestricted write accesses.
- 25 -
Publication Release Date: February 1, 2007
Revision A8
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