W79E804ADG 参数 Datasheet PDF下载

W79E804A/803A/802A

any errant code is executed now, then the reset Watchdog Timer instructions will not be executed at

the required instants and Watchdog reset will occur.

The Watchdog Timer time-out selection will result in different time-out values depending on the clock

speed. The reset, when enabled, will occur when 512 clocks after time-out has occurred.

RESET

TIME-OUT

WD1

WD0

INTERRUPT

TIME-OUT

NUMBER OF

CLOCKS

TIME

@ 10 MHZ

0

0

1

1

0

1

0

1

2

17

2

20

2

23

2

26

2

17

+ 512

2

20

+ 512

2

23

+ 512

2

26

+ 512

131072

1048576

8388608

67108864

13.11 mS

104.86 mS

838.86 mS

6710.89 mS

Table 15-2: Time-out values for the Watchdog Timer

The Watchdog Timer will be disabled by a power-on/fail reset. The Watchdog Timer reset does not

disable the Watchdog Timer, but will restart it. In general, software should restart the timer to put it into

a known state. The control bits that support the Watchdog Timer are discussed below.

15.1 WATCHDOG CONTROL

WDIF: WDCON.3 - Watchdog Timer Interrupt flag. This bit is set whenever the time-out occurs in the

Watchdog Timer. If the Watchdog interrupt is enabled (EIE.4), then an interrupt will occur (if the global

interrupt enable is set and other interrupt requirements are met). Software or any reset can clear this

bit.

WTRF: WDCON.2 - Watchdog Timer Reset flag. This bit is set whenever a watchdog reset occurs.

This bit is useful for determined the cause of a reset. Software must read it, and clear it manually. A

Power-fail reset will clear this bit. If EWRST = 0, then this bit will not be affected by the Watchdog

Timer.

EWRST: WDCON.1 - Enable Watchdog Timer Reset. This bit when set to 1 will enable the Watchdog

Timer reset function. Setting this bit to 0 will disable the Watchdog Timer reset function, but will leave

the timer running.

WDCLR: WDCON.0 - Reset Watchdog Timer. This bit is used to clear the Watchdog Timer and to

restart it. This bit is self-clearing, so after the software writes 1 to it the hardware will automatically

clear it. If the Watchdog Timer reset is enabled, then the WDCLR has to be set by the user within 512

clocks of the time-out. If this is not done then a Watchdog Timer reset will occur.

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