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W79E804ADG 参数 Datasheet PDF下载

W79E804ADG图片预览
型号: W79E804ADG
PDF下载: 下载PDF文件 查看货源
内容描述: 8位微控制器 [8-BIT MICROCONTROLLER]
分类和应用: 微控制器和处理器外围集成电路光电二极管时钟
文件页数/大小: 115 页 / 1566 K
品牌: WINBOND [ WINBOND ]
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W79E804A/803A/802A
24.3.3 Slave Receiver Mode
Serial data and the serial clock are received through SDA and SCL. After each byte is received, an
acknowledge bit is transmitted. START and STOP conditions are recognized as the beginning and
end of a serial transfer. Address recognition is performed by hardware after reception of the slave
address and direction bit.
24.3.4 Slave Transmitter Mode
The first byte is received and handled as in the slave receiver mode. However, in this mode, the
direction bit will indicate that the transfer direction is reversed. Serial data is transmitted via SDA while
the serial clock is input through SCL. START and STOP conditions are recognized as the beginning
and end of a serial transfer.
24.4 Data Transfer Flow in Five Operating Modes
The five operating modes are: Master/Transmitter, Master/Receiver, Slave/Transmitter,
Slave/Receiver and GC Call. Bits STA, STO and AA in I2CON register will determine the next state of
the SIO hardware after SI flag is cleared. Upon complexion of the new action, a new status code will
be updated and the SI flag will be set. If the I2C interrupt control bits (EA and EI2) are enable,
appropriate action or software branch of the new status code can be performed in the Interrupt service
routine.
Data transfers in each mode are shown in the following figures.
*** Legend for the following five figures:
Software's access to S1DAT with respect to "Expected next action":
08H
(1) Data byte will be transmitted:
A START has been
Software should load the data byte (to be transmitted)
transmitted.
into S1DAT before new S1CON setting is done.
(2) SLA+W (R) will be transmitted:
Software should load the SLA+W/R (to be transmitted)
into S1DAT before new S1CON setting is done.
(STA,STO,SI,AA)=(0,0,0,X)
(3) Data byte will be received:
Software can read the received data byte from S1DAT
SLA+W will be transmitted;
while a new state is entered.
ACK bit will be received.
Last state
Last action is done
Next setting in S1CON
Expected next action
New state
next action is done
18H
SLA+W has been transmitted;
ACK has been received.
Figure 24-3: Legen for the following four figures
- 99 -
Publication Release Date: July 16, 2007
Revision A2