W79E532/W79L532
Clock Control
Bit:
7
6
5
4
3
2
1
0
WD1
WD0
T2M
T1M
T0M
MD2
MD1
MD0
Mnemonic: CKCON
Address: 8Eh
WD1−0: Watchdog timer mode select bits: These bits determine the time-out period for the watchdog
timer. In all four time-out options the reset time-out is 512 clocks more than the interrupt time-
out period.
WD1 WD0
Interrupt time-out
Reset time-out
217 + 512
217
220
223
226
0
0
1
1
0
1
0
1
220 + 512
223 + 512
226 + 512
T2M: Timer 2 clock select: When T2M is set to 1, timer 2 uses a divide by 4 clock, and when set to
0 it uses a divide by 12 clock.
T1M: Timer 1 clock select: When T1M is set to 1, timer 1 uses a divide by 4 clock, and when set to
0 it uses a divide by 12 clock.
T0M: Timer 0 clock select: When T0M is set to 1, timer 0 uses a divide by 4 clock, and when set to
0 it uses a divide by 12 clock.
MD2−0: Stretch MOVX select bits: These three bits are used to select the stretch value for the MOVX
instruction. Using a variable MOVX length enables the user to access slower external
memory devices or peripherals without the need for external circuits. The RD or WR strobe
will be stretched by the selected interval. When accessing the on-chip SRAM, the MOVX
instruction is always in 2 machine cycles regardless of the stretch setting. By default, the
stretch has value of 1. If the user needs faster accessing, then a stretch value of 0 should be
selected.
MD2 MD1 MD0 Stretch value MOVX duration
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
0
1
2
3
4
5
6
7
2 machine cycles
3 machine cycles (Default)
4 machine cycles
5 machine cycles
6 machine cycles
7 machine cycles
8 machine cycles
9 machine cycles
Publication Release Date: November 21, 2005
Revision A5
- 13 -
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