W83195R-08
PRELIMINARY
5.3 I C Control Interface
SYMBOL
*SDATA
*SDCLK
PIN
27
28
I/O
I/O
IN
FUNCTION
Serial data of I
2
C 2-wire control interface with internal
pull-up resistor.
Serial clock of I
2
C 2-wire control interface with
internal pull-up resistor.
2
5.4 Fixed Frequency Outputs
SYMBOL
REF0 / PCI_STOP#
PIN
3
I/O
I/O
FUNCTION
14.318MHz reference clock. This REF output is the
stronger buffer for ISA bus loads.
Halt PCICLK(0:4) clocks at logic 0 level, when input
low (In mobile mode. MODE=0)
REF1 / *FS2
2
I/O
14.318MHz reference clock.
Latched input for FS2 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
24MHz / *FS0
30
I/O
24MHz output clock.
Latched input for FS1 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
48MHz / *FS1
29
I/O
48MHz output for USB during normal operation.
Latched input for FS0 at initial power up for H/W
selecting the output frequency of CPU, SDRAM and
PCI clocks.
5.5 Power Pins
SYMBOL
Vddq1
VddL1
VddL2
Vddq2
Vddq3
Vddq4
Vss
PIN
1
56
50
7,15
20,37,45
31
FUNCTION
Power supply for Ref [0:1] crystal and core logic.
Power supply for IOAPIC output, either 2.5V or 3.3V.
Power supply for CPUCLK_F & CPUCLK[1:2], either
2.5V or 3.3V.
Power supply for PCICLK_F, PCICLK[0:5], 3.3V.
Power supply for SDRAM_F & SDRAM[0:15], and CPU
PLL core, nominal 3.3V.
Power for 24 & 48MHz output buffers and fixed PLL
core.
4,10,23,26,34,42,48, Circuit Ground.
53
Publication Release Date: Mar. 1999
Revision 0.30
-4-
WINBOND [ WINBOND ]
