W83195R-08
PRELIMINARY
8.3.5 Register 4: Reserved Register (1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@PowerUp
X
1
1
1
x
1
x
1
Pin
-
-
-
-
-
-
-
-
Latched FS0#
Reserved
Reserved
Reserved
Latched FS1#
Reserved
Latched FS3#
Reserved
Description
8.3.6 Register 5: Peripheral Control (1 = enable, 0 = Stopped)
Bit
7
6
5
4
3
2
1
0
@PowerUp
1
X
1
1
1
1
1
1
Pin
-
-
-
54
55
-
2
3
Reserved
Latched FS2#
Reserved
IOAPIC _F(Active / Inactive)
IOAPIC0 (Active / Inactive)
Reserved
REF1 (Active / Inactive)
REF0 (Active / Inactive)
Description
-9-
Publication Release Date: Mar. 1999
Revision 0.30