W981616AH
PIN DESCRIPTION
PIN NUMBER
20−24,
27−32
19
PIN NAME
A0−A10
BA
FUNCTION
Address
Bank Select
DESCRIPTION
Multiplexed pins for row and column address.
Row address: A0−A10. Column address: A0−A7.
Select bank to activate during row address latch time,
or bank to read/write during column address latch
time.
Multiplexed pins for data input and output.
2, 3, 5, 6, 8, 9, DQ0−DQ15
11, 12, 39, 40,
42, 43, 45, 46,
48, 49
18
CS
Data Input/
Output
Chip Select
Disable or enable the command decoder. When
command decoder is disabled, new command is
ignored and previous operation continues.
Command input. When sampled at the rising edge of
the clock,
RAS
,
CAS
and
WE
define the operation to
be executed.
17
RAS
Row Address
Strobe
16
15
36, 14
CAS
WE
Column
Referred to
RAS
Address Strobe
Write Enable
Input/Output
Mask
Referred to
RAS
The output buffer is placed at Hi-Z (with latency of 2)
when DQM is sampled high in read cycle. In write
cycle, sampling DQM high will block the write
operation with zero latency.
System clock used to sample inputs on the rising
edge of clock.
CKE controls the clock activation and deactivation.
W hen CKE is low, Power Down mode, Suspend
mode, or Self Refresh mode is entered.
Ground for input buffers and logic circuit inside
DRAM.
UDQM/
LDQM
35
34
CLK
CKE
Clock Inputs
Clock Enable
1, 25
26, 50
7, 13, 38, 44,
4, 10, 41, 47
33, 37
V
CC
V
SS
V
CC
Q
V
SS
Q
NC
Power (+3.3V) Power for input buffers and logic circuit inside DRAM.
Ground
Power (+3.3V) Separated power from V
CC
, used for output buffers to
for I/O buffer improve noise immunity.
Ground for I/O Separated ground from V
SS
, used for output buffers
buffer
to improve noise immunity.
No Connection No connection
-2-
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