W986408CH
2M x 8 bit x 4 Banks SDRAM
Pin Assignment
Pin Number Pin Name
Function
23 ~ 26, 22,
A0~ A11
Address
29 ~35
20, 21
BS0, BS1
Bank Select
Data Input/
Output
Chip Select
Row Address
Strobe
Column Address
Strobe
Write Enable
Description
Multiplexed pins for row and column address.
Row address : A0 ~ A11. Column address: A0 ~ A8.
Select bank to activate during row address latch time, or bank
to read/write during address latch time.
Multiplexed pins for data output and input.
Disable or enable the command decoder. When command
decoder is disabled, new command is ignored and previous
operation continues.
Command input. When sampled at the rising edge of the clock,
RAS#, CAS# and WE# define the operation to be executed.
Referred to RAS#
2, 5, 8, 11,
DQ0 ~ DQ7
44, 47, 50, 53
19
18
17
16
39
38
37
1, 14, 27
28, 41, 54
3, 9, 43, 49
6, 12, 46, 52
CS#
RAS#
CAS#
WE#
DQM
CLK
CKE
V
CC
V
SS
V
CC
Q
V
SS
Q
Referred to RAS#
The output buffer is placed at Hi-Z(with latency of 2) when DQM
input/output mask is sampled high in read cycle. In write cycle, sampling DQM
high will block the write operation with zero latency.
Clock Inputs
System clock used to sample inputs on the rising edge of clock.
CKE controls the clock activation and deactivation. When CKE
Clock Enable
is low, Power Down mode, Suspend mode, or Self Refresh
mode is entered.
Power ( +3.3 V ) Power for input buffers and logic circuit inside DRAM.
Ground
Ground for input buffers and logic circuit inside DRAM.
Power ( + 3.3 V ) Separated power from V
CC
, used for output buffers to improve
for I/O buffer
noise.
Ground for I/O
Separated ground from V
SS
, used for output buffers to improve
buffer
noise.
No Connection
No connection
4, 7, 10, 13,
15, 36, 40, 42, NC
45, 48, 51
Revision 1.0
-3-
Publication Release Date: March, 1999
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