W9864G2GH
10.5
Mode Register Set Cycle
t
RSC
CLK
t
CMS
t
CMH
CS
t
CMS
t
CMH
RAS
t
CMS
t
CMH
CAS
t
CMS
t
CMH
WE
t
AS
t
AH
Register
set data
A0-A10
BS0,1
A0
A1
A2
A3
A4
A5
A6
A0
A7
A8
A0
A9
A10
A0
BS0
BS1
"0"
"0"
"0"
Reserved
"0"
"0"
(Test Mode)
Reserved
A0
Write Mode
CAS Latency
Addressing Mode
Burst Length
A2
0
0
0
0
1
1
1
1
A0
A0
A1
A0
0
A0
0
A0
1
A0
1
A0
0
A0
0
A0
1
A0
1
A3
A0
A0
0
A0
1
A0
0
1
0
1
0
1
0
1
next
command
BurstA0
Length
A0
A0
Sequential
Interleave
1
A0
1
A0
2
A0
2
A0
A0
4
4
A0
A0
8
8
A0
Reserved
FullA0
Page
Addressing Mode
A0
A0
Sequential
Interleave
A0
A0
Reserved
A6
0
0
0
0
1
A0
A5
A0
0
A0
0
A0
1
A0
1
A0
0
A0
A9
A0
0
A0
1
A4
0
1
0
1
0
CAS A0
Latency
A0
Reserved
Reserved
A0
2
A0
3
Reserved
Single Write Mode
Burst read and Burst write
A0
A0
Burst read and single write
- 24 -
Publication Release Date:Aug. 13, 2007
Revision A09
WINBOND [ WINBOND ]
