W9864G2GH
11. OPERATING TIMING EXAMPLE
11.1 Interleaved Bank Read (Burst Length = 4, CAS Latency = 3)
(CLK = 100 MHz)
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
1
2
3
4
5
0
CLK
CS
t
RC
tRC
t
RC
tRC
RAS
CAS
WE
t
RAS
t
RP
t
RAS
RP
tRP
t
RAS
t
tRAS
BS0
BS1
t
RCD
t
RCD
t
RCD
t
RCD
RAa
RAa
RBb
RAc
RAc
RBd
RBd
A10
RAe
RAe
CAw
CBx
RBb
CAy
CBz
A0-A9
DQM
CKE
DQ
t
AC
t
AC
t
AC
t
AC
cy2
bx1
bx3
aw0
aw2 aw3
bx0
bx2
cy1
cy3
aw1
cy0
t
RRD
t
RRD
tRRD
t
RRD
Precharge
Read
Active
Read
Precharge
Active
Bank #0
Bank #1
Bank #2
Read
Active
Precharge
Read
Active
Active
Idle
Bank #3
Publication Release Date:Aug. 13, 2007
Revision A09
- 25 -
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