Production Data
WM2626
SERIAL INTERFACE
t
WL
SCLK
1
t
SUD
DIN
D15
t
SUCSCK
NCS
t
HD
D14
D13
D12
D1
D0
2
t
WH
3
4
5 15
16
t
SUC16CS
Figure 1 Timing Diagram
Test Conditions:
R
L
= 10kΩ, C
L
= 100pF. VDD = 5V
±
10%, V
REF
= 2.048V and VDD = 3V
±
10%, V
REF
= 1.024V over recommended operating
free-air temperature range (unless noted otherwise).
SYMBOL
t
SUCSCK
t
SUC16CS
t
WH
t
WL
t
SUD
t
HD
TEST CONDITIONS
Setup time, NCS low before first falling SCLK edge
Setup time, 16 falling SCLK edge (when data bit D0
is sampled) before NCS rising edge.
Pulse duration, SCLK high.
Pulse duration, SCLK low.
Setup time, data ready before SCLK falling edge.
Hold time, data held valid after SCLK falling edge.
th
MIN
10
10
25
25
10
5
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
5
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
