Production Data
WM2626
DEVICE DESCRIPTION
GENERAL FUNCTION
The WM2626 is a dual 8-bit, voltage output DAC with an on-chip voltage reference. It uses a
resistor string network buffered with an op amp to convert 8-bit digital data to analogue voltage
levels (see Block Diagram). The output voltage is determined by the reference voltage and the
input code according to the following relationship:
CODE
V
= 2
(VREFIN
)
out
256
INPUT
OUTPUT
255
256
1111
1111
2
2
(
VREF
)
:
:
129
256
1000
1000
0111
0001
0000
1111
(VREF
)
128
256
2
(
VREF
)
= VREF
127
256
2
2
(VREF
)
)
:
:
1
0000
0000
0001
0000
(VREF
256
0V
Table 1 Binary Code Table (0V to 2VREF Output), Gain = 2
POWER ON RESET
An internal power-on-reset circuit resets the DAC register to all 0s on power-up.
BUFFER AMPLIFIER
The output buffer has a near rail-to-rail output with short circuit protection and can reliably drive a
2kΩ load with a 100pF load capacitance.
SERIAL INTERFACE
Before writing any data to the WM2626, the interface must be enabled by setting NCS to low.
Incoming data on DIN (starting with the MSB) is then shifted bit-per-bit into the internal register on
the falling edges of SCLK. From there data is loaded into the target latch after 16 bits have been
transferred, or when NCS rises. Four internal latches can be addressed: DAC A, DAC B, the buffer
latch or the control register. Their function is explained below (see ‘Register Addressing’).
SERIAL CLOCK AND UPDATE RATE
Figure 1 shows the device timing. The maximum serial rate is:
1
fSCLK max
=
= 20MHz
tWH min + tWLmin
Since a data word contains 16 bits, the sample rate for one channel is limited to
1
fs max
=
= 1.25MHz
16×
(
tWH min + tWLmin
)
For full two-channel operation, where two data words need to be transmitted per sample, this figure
is halved to 625kHz. However, the DAC settling time to 8-bit accuracy limits the response time of
the analogue output for large input step transitions.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
7
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
