WM2629
SERIAL INTERFACE
Production Data
t
WL
SCLK
X
t
SUD
DIN
DOUT
X
X
D15
D15 *
1
2
t
HD
D14
D14 *
t
WH
3
4
16
X
D13
D13 *
2
D12 *
D1
D1 *
D0
D0 *
t
SUC16-FS
X
X
t
WHFS
t
SUFSCLK
FS
(µC MODE)
t
WLFS
FS
(DSP MODE)
* DIN data from previous word
(delayed by 16 clock cycles)
No high to low transitions
Figure 1 Timing Diagram
SYMBOL
t
SUFSCLK
t
C16-FS
t
WLOADB
t
WH
t
WL
t
SUD
t
HD
t
WHFS
t
WLFS
t
s
TEST
CONDITIONS
Setup time, FS pin low before first falling edge of SCLK
Setup time, 16
th
falling clock edge after FS low to rising edge of FS
(only used in microcontroller mode)
Pulse duration, LOADB low
Pulse duration, SCLK high
Pulse duration, SCLK low
Setup time, data ready before SCLK falling edge
Hold time, data held valid after SCLK falling edge
Pulse duration, FS high
Pulse duration, FS low
DAC Output settling time
MIN
8
10
10
16
16
8
5
10
10
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
see Dynamic DAC Specifications
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 April 2001
6
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
