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WM2638 参数 Datasheet PDF下载

WM2638图片预览
型号: WM2638
PDF下载: 下载PDF文件 查看货源
内容描述: 双路12位串行输入电压输出DAC ,内置基准 [Dual 12-Bit Serial Input Voltage Output DAC with Internal reference]
分类和应用:
文件页数/大小: 11 页 / 363 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM2638
Production Data
Test Conditions:
R
L
= 10kΩ, C
L
= 100pF. VDD = 5V
±
10%, V
REF
= 2.048V and VDD = 3V
±
10%, V
REF
= 1.024V over recommended operating free-air
temperature range (unless noted otherwise)
PARAMETER
Total harmonic distortion
SYMBO
L
THD
TEST CONDITIONS
fs = 400ksps, f
OUT
= 1kHz,
BW = 20kHz
See Note 12
fs = 400ksps, f
OUT
= 1kHz,
BW = 20kHz
See Note 12
MIN
TYP
-69
MAX
-57
UNIT
dB
Spurious free dynamic range
SPFDR
57
72
dB
Reference configured as input
Reference input resistance
Reference input capacitance
Reference feedthrough
Reference input bandwidth
R
REFIN
C
REFIN
V
REF
= 1V
PP
at 1kHz
+ 1.024V dc, DAC code 0
V
REF
= 0.2V
PP
+ 1.024V dc
DAC code 2048
Slow
Fast
V
REFOUTL
V
REFOUTH
I
REFSRC
I
REFSNK
-1
100
-48
VDD > 4.75V
1.003
2.027
10
55
-60
MΩ
pF
dB
1.0
1.0
1.024
2.048
1.045
2.069
1
MHz
MHz
V
V
mA
mA
pF
dB
µA
µA
pF
Reference configured as output
Low reference voltage
High reference voltage
Output source current
Output sink current
Load Capacitance
PSRR
Digital Inputs
High level input current
Low level input current
Input capacitance
Notes:
1.
I
IH
I
IL
C
I
Input voltage = VDD
Input voltage = 0V
8
1
-1
Integral non-linearity (INL)
is the maximum deviation of the output from the line between zero and full scale (excluding the
effects of zero code and full scale errors).
2.
Differential non-linearity (DNL)
is the difference between the measured and ideal 1LSB amplitude change of any adjacent two
codes. A guarantee of monotonicity means the output voltage changes in the same direction (or remains constant) as a change
in digital input code.
3.
Zero code error
is the voltage output when the DAC input code is zero.
4.
Gain error
is the deviation from the ideal full scale output excluding the effects of zero code error.
5.
Power supply rejection ratio
is measured by varying VDD from 4.5V to 5.5V and measuring the proportion of this signal
imposed on the zero code error and the gain error.
6.
Zero code error
and
Gain error
temperature coefficients are normalised to full scale voltage.
7.
Output load regulation
is the difference between the output voltage at full scale with a 10kΩ load and 2kΩ load. It is expressed
as a percentage of the full scale output voltage with a 10kΩ load.
8.
I
DD
is measured while continuously writing code 2048 to the DAC. For V
IH
< VDD - 0.7V and V
IL
> 0.7V supply current will
increase.
9.
Typical supply current
in power down mode is 10nA. Production test limits are wider for speed of test.
10.
Slew rate
results are for the lower value of the rising and falling edge slew rates
11.
Settling time
is the time taken for the signal to settle to within 0.5LSB of the final measured value for both rising and falling
edges. Limits are ensured by design and characterisation, but are not production tested.
12.
SNR, SNRD, THD
and
SPFDR
are measured on a synthesised sinewave at frequency f
OUT
generated with a sampling frequency
fs.
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
4