WM2638
SERIAL INTERFACE
Production Data
t
SUCSS
NCS
t
WCL
SCLK
t
SUDCLK
DIN
D15
D14
t
HDCLK
D13
D12
D11
D0
t
WCH
t
SUCS1
t
SUCS2
Figure 1 Timing Diagram
Test Conditions:
R
L
= 10kΩ, C
L
= 100pF. VDD = 5V
±
10%, V
REF
= 2.048V and VDD = 3V
±
10%, V
REF
= 1.024V over recommended operating free-
air temperature range (unless noted otherwise)
SYMBOL
t
SUCSS
t
SUSCS1
t
SUSCS2
t
WCL
t
WCH
t
SUDCLK
t
HDCLK
TEST CONDITIONS
Setup time NCS low before SCLK low
Setup time, rising edge of SCLK to rising edge of NCS,
external end of write
Setup time, rising edge of SCLK to falling edge of NCS,
start of next write cycle
Pulse duration, SCLK high
Pulse duration, SCLK low
Setup time, data ready before SCLK falling edge
Hold time, data held valid after SCLK falling edge
MIN
10
10
5
25
25
10
5
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
WOLFSON MICROELECTRONICS LTD
PD Rev 1.0 July 99
5
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
