WM8196
PIN DESCRIPTION
PIN
1
2
3
4
5
6
7
8
9
10
11
12
NAME
RINP
AGND2
DVDD1
OEB
VSMP
RLC/ACYC
MCLK
DGND
SEN
DVDD2
SDI
SCK
TYPE
Analogue input
Supply
Supply
Digital input
Digital input
Digital input
Digital input
Supply
Digital input
Supply
Digital input
Digital input
DESCRIPTION
Red channel input video.
Analogue ground (0V).
Production Data
Digital supply (5V) for logic and clock generator. This must be operated at the same
potential as AVDD.
Output Hi-Z control, all digital outputs disabled when OEB = 1.
Video sample synchronisation pulse.
RLC (active high) selects reset level clamp on a pixel-by-pixel basis – tie high if
used on every pixel. ACYC autocycles between R, G, B inputs.
Master clock. This clock is applied at N times the input pixel rate (N = 2, 3, 6, 8 or
any multiple of 2 thereafter depending on input sample mode).
Digital ground (0V).
Enables the serial interface when high.
Digital supply (5V/3.3V), all digital I/O pins.
Serial data input.
Serial clock.
Digital multiplexed output data bus.
ADC output data (d15:d0) is available in two multiplexed formats as shown, under
the control of register MUXOP [1:0]
See ‘Output Formats’ description in Device Description section for further details.
8+8-bit
A
B
d0
d1
d2
d3
d4
d5
d6
d7
d12
d13
d14
d15
d8
d9
d10
d11
d4
d5
d6
d7
d0
d1
d2
d3
A
B
4+4+4+4-bit
C
D
13
14
15
16
17
18
19
20
OP[0]
OP[1]
OP[2]
OP[3]
OP[4]
OP[5]
OP[6]
OP[7]/SDO
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
Digital output
d8
d9
d10
d11
d12
d13
d14
d15
Alternatively, pin OP[7]/SDO may be used to output register read-back data when
OEB = 0 and SEN has been pulsed high. See Serial Interface description in Device
Description section for further details.
21
22
23
24
25
26
AVDD
AGND1
VRB
VRT
VRX
VRLC/VBIAS
Supply
Supply
Analogue output
Analogue output
Analogue output
Analogue I/O
Analogue supply (5V). This must be operated at the same potential as DVDD1.
Analogue ground (0V).
Lower reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Upper reference voltage.
This pin must be connected to AGND via a decoupling capacitor.
Input return bias voltage.
This pin must be connected to AGND via a decoupling capacitor.
Selectable analogue output voltage for RLC or single-ended bias reference.
This pin would typically be connected to AGND via a decoupling capacitor.
VRLC can be externally driven if programmed Hi-Z.
Blue channel input video.
Green channel input video.
27
28
BINP
GINP
Analogue input
Analogue input
w
PD Rev 4.3 March 2007
4
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
