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WM8510GEDS/V 参数 Datasheet PDF下载

WM8510GEDS/V图片预览
型号: WM8510GEDS/V
PDF下载: 下载PDF文件 查看货源
内容描述: 单声道编解码器与扬声器驱动器 [MONO CODEC WITH SPEAKER DRIVER]
分类和应用: 解码器驱动器编解码器
文件页数/大小: 56 页 / 558 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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WM8510
INPUT PGA VOLUME CONTROL
Product Preview
The input microphone PGA has a gain range from -12dB to +35.25dB in 0.75dB steps. The gain
from the MICN input to the PGA output and from the MIC2 amplifier to the PGA output are always
common and controlled by the register bits INPPGAVOL[5:0]. These register bits also affect the
MICP pin when MICP2INPPGA=1.
When the Automatic Level Control (ALC) is enabled the input PGA gain is then controlled
automatically and the INPPGAVOL bits should not be used.
REGISTER
ADDRESS
R45
Input PGA
volume
control
BIT
5:0
LABEL
INPPGAVOL
DEFAULT
010000
DESCRIPTION
Input PGA volume
000000 = -12dB
000001 = -11.25db
.
010000 = 0dB
.
111111 = +35.25dB
Mute control for input PGA:
0=Input PGA not muted, normal operation
1=Input PGA muted (and disconnected
from the following input BOOST stage).
Input PGA zero cross enable:
0=Update gain when gain register
changes
1=Update gain on 1
st
zero cross after gain
register write.
ALC function select:
0=ALC off (PGA gain set by INPPGAVOL
register bits)
1=ALC on (ALC controls PGA gain)
6
INPPGAMUT
E
0
7
INPPGAZC
0
R32
ALC control
1
8
ALCSEL
0
Table 1 Input PGA Volume Control
MIC 2 INPUT
A second mic input circuit, MIC2 (Figure 7) is provided which consists of an amplifier which can be
configured either as an inverting buffer for a single input signal or as a mixer/summer for multiple
inputs with the use of external resistors. The circuit is enabled by the register bit MIC2EN.
Figure 7 MIC2 Input Circuit
The MIC2MODE register bit controls the input mode of operation:
In buffer mode (MIC2MODE=0) the switch labelled MIC2SW in Figure 7 is open and the signal at the
MIC2 pin will be buffered and inverted through the MIC2 circuit using only the internal components.
w
PP Rev 1.2 December 2004
16