WM8521
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1/fs
Max 4 BCLKs
LRCLK
BCLK
LEFT CHANNEL
DIN
1
MSB
2
15 16
LSB
1
2
RIGHT CHANNEL
15 16
NO VALID DATA
1
MSB
Input Word Length (16 bits)
Figure 5 DSP ‘Late’ Mode Timing
1 BCLK
1/fs
Max 4 BCLKs
LRCLK
1 BCLK
BCLK
LEFT CHANNEL
DIN
1
MSB
2
15 16
LSB
1
RIGHT CHANNEL
2
15 16
NO VALID DATA
Input Word Length (16 bits)
Figure 6 DSP ‘Early’ Mode Timing
AUDIO DATA SAMPLING RATES
The master clock for WM8521 supports audio sampling rates from 256fs to 768fs, where fs is the
audio sampling frequency (LRCLK) typically 32kHz, 44.1kHz, 48kHz or 96kHz. The master clock is
used to operate the digital filters and the noise shaping circuits.
The WM8521 has a master clock detection circuit that automatically determines the relationship
between the master clock frequency and the sampling rate (to within +/- 32 master clocks). If there is
a greater than 32 clocks error, the master clock defaults to 768fs. The master clock should be
synchronised with LRCLK, although the WM8521 is tolerant of phase differences or jitter on this
clock.
SAMPLING
RATE
(LRCLK)
32kHz
44.1kHz
48kHz
96kHz
MASTER CLOCK FREQUENCY (MHz) (MCLK)
256fs
8.192
11.2896
12.288
24.576
384fs
12.288
16.9344
18.432
36.864
512fs
16.384
22.5792
24.576
Unavailable
768fs
24.576
33.8688
36.864
Unavailable
Table 1 Master Clock Frequencies Versus Sampling Rate
Note:
For sample rates down to 8k, scale MCLK accordingly.
w
PP Rev 1.3 December 2004
12
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
