WM8522
MPU INTERFACE TIMING
Production Data
Figure 6 SPI Compatible Control Interface Input Timing
Test Conditions
AVDD = 5V, DVDD = 3.3V, AGND, DGND = 0V, T
A
= +25
o
C, fs = 48kHz, MCLK = 256fs unless otherwise stated
PARAMETER
SCLK/IWL rising edge to CSB/I2S rising edge
SCLK/IWL pulse cycle time
SCLK/IWL pulse width low
SCLK/IWL pulse width high
SDIN/DM to SCLK/IWL set-up time
SCLK/IWL to SDIN/DM hold time
CSB/I2S pulse width low
CSB/I2S pulse width high
CSB/I2S rising to SCLK/IWL rising
SYMBOL
t
SCS
t
SCY
t
SCL
t
SCH
t
DSU
t
DHO
t
CSL
t
CSH
t
CSS
MIN
60
80
30
30
20
20
20
20
20
TYP
MAX
UNIT
ns
ns
ns
ns
ns
ns
ns
ns
ns
Table 4 3-Wire SPI Compatible Control Interface Input Timing Information
w
PD Rev 4.0 July 2006
10
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
