WM8522
DIGITAL AUDIO INTERFACE – MASTER MODE
Production Data
BCLK
WM8522
DAC
LRCLK
DIN1/2/3
3
DSP/
DECODER
Figure 2 Audio Interface - Master Mode
BCLK
(Output)
t
DL
LRCLK
(Output)
DIN1/2/3
t
DST
Figure 3 Digital Audio Data Timing – Master Mode
Test Conditions
AVDD, VREFP = 5V, DVDD = 3.3V, AGND, VREFN, DGND = 0V, T
A
= +25
o
C, Master Mode, fs = 48kHz, MCLK = 256fs unless
otherwise stated.
PARAMETER
LRCLK propagation delay
from BCLK falling edge
DIN1/2/3 setup time to
BCLK rising edge
DIN1/2/3 hold time from
BCLK rising edge
SYMBOL
t
DL
t
DST
t
DHT
TEST CONDITIONS
MIN
0
10
10
TYP
MAX
10
UNIT
ns
ns
ns
t
DHT
Audio Data Input Timing Information
Table 2 Digital Audio Data Timing – Master Mode
w
PD Rev 4.0 July 2006
8
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
