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WM8580GEFT/RV 参数 Datasheet PDF下载

WM8580GEFT/RV图片预览
型号: WM8580GEFT/RV
PDF下载: 下载PDF文件 查看货源
内容描述: 多通道编解码器S / PDIF收发器 [Multichannel CODEC with S/PDIF Transceiver]
分类和应用: 解码器编解码器光电二极管
文件页数/大小: 92 页 / 960 K
品牌: WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
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Production Data
WM8580
TYPE
Digital Input/Output
Digital Input
Digital Input
Digital Output
Digital Input/Output
Digital Input/Output
Digital Input
Digital Output
Digital Input
Digital Input
Digital Output
Digital Output
DESCRIPTION
Primary Audio Interface Transmitter (PAIFTX) Bit Clock
Master ADC clock; 256fs, 384fs, 512fs ,786fs, 1024fs or 1152fs
Secondary Audio Interface (SAIF) Receiver data input
Secondary Audio Interface (SAIF) Transmitter data output
Secondary Audio Interface (SAIF) Bit Clock
Secondary Audio Interface (SAIF) Left/Right Word Clock
S/PDIF Receiver Input
General Purpose Output
Internal Digital Routing Configuration in Hardware Mode
Chip Powerdown in Hardware Mode
Recovered channel-bit for current S/PDIF sub-frame
Indicates current S/PDIF sub-frame:
1 = Sub-frame A
0 = Sub-frame B
Indicates start of S/PDIF 192-frame block. High for duration of frame 0.
PIN FUNCTION
PAIFTX_BCLK
ADCMCLK
SAIF_DIN
SAIF_DOUT
SAIF_BCLK
SAIF_LRCLK
SPDIFIN2/3/4
GPO1 – GPO10
DR1/2/3/4
ALLPD
C
SFRM_CLK
192BCLK
Digital Output
Table 2 Multi-Function Pin Description
ABSOLUTE MAXIMUM RATINGS
Absolute Maximum Ratings are stress ratings only. Permanent damage to the device may be caused by continuously operating at
or beyond these limits. Device functional operating limits and guaranteed performance specifications are given under Electrical
Characteristics at the test conditions specified.
ESD Sensitive Device. This device is manufactured on a CMOS process. It is therefore generically susceptible
to damage from excessive static voltages. Proper ESD precautions must be taken during handling and storage
of this device.
The WM8580 has been classified as MSL1, which has an unlimited floor life at <30
o
C / 85% Relative Humidity and therefore will
not be supplied in moisture barrier bags.
CONDITION
Digital supply voltage
Analogue supply voltage
PLL supply voltage
Voltage range digital inputs (SCLK, CSB & SDIN only)
Voltage range digital inputs
Voltage range analogue inputs
Master Clock Frequency
Operating temperature range, T
A
Storage temperature prior to soldering
Storage temperature after soldering
Pb Free Package body temperature (soldering 10 seconds)
Package body temperature (soldering 2 minutes)
Notes:
1. Analogue and digital grounds must always be within 0.3V of each other.
-25°C
-65°C
1
MIN
-0.3V
-0.3V
-0.3V
DGND -0.3V
DGND -0.3V
AGND -0.3V
PGND -0.3V
MAX
+3.63V
+7V
+5V
+7V
DVDD + 0.3V
AVDD +0.3V
PVDD +0.3V
37MHz
+85°C
+150°C
+260°C
+183°C
30°C max / 85% RH max
w
PD Rev 4.0 February 2007
7