WM8711BLGEFL/RV 参数 Datasheet PDF下载

WM8711BL

PIN DESCRIPTION

PIN

1

2

3

4

5

6

7

8

9

10

11

12

13

14

15

16

17

18

19

20

21

22

23

24

Note:

1.

2.

Pull Up/Down only present when Control Register Interface ACTIVE=0 to conserve power.

It is recommended that the QFN ground paddle is connected to analogue ground on the application PCB.

NAME

XTI/MCLK

XTO

DCVDD

DGND

DBVDD

CLKOUT

BCLK

DACDAT

DACLRC

HPVDD

LHPOUT

RHPOUT

HPGND

LOUT

ROUT

AVDD

AGND

VMID

RLINEIN

LLINEIN

MODE

CSB

SDIN

SCLK

TYPE

Digital Input

Digital Output

Supply

Ground

Supply

Digital Output

Digital Input/Output

Digital Input

Digital Input/Output

Supply

Analogue Output

Analogue Output

Ground

Analogue Output

Analogue Output

Supply

Ground

Analogue Output

Analogue Input

Analogue Input

Digital Input

Digital Input

Digital Input/Output

Digital Input

Crystal Output

Digital Core VDD

Digital GND

Digital Buffers VDD

Buffered Clock Output

Digital Audio Bit Clock, Pull Down (see Note 1)

DAC Digital Audio Data Input

DESCRIPTION

Crystal Input or Master Clock Input (MCLK)

Production Data

DAC Sample Rate Left/Right Clock, Pull Down (see Note 1)

Headphone VDD

Left Channel Headphone Output

Right Channel Headphone Output

Headphone GND

Left Channel Line Output

Right Channel Line Output

Analogue VDD

Analogue GND

Mid-rail reference decoupling point

Right Channel Line Input (AC coupled)

Left Channel Line Input (AC coupled)

Control Interface Selection, Pull up (see Note 1)

3-Wire MPU Chip Select/ 2-Wire MPU interface address

selection, active low, Pull up (see Note 1)

3-Wire MPU Data Input / 2-Wire MPU Data Input

3-Wire MPU Clock Input / 2-Wire MPU Clock Input

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PD, Rev 4.1, April 2007

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