WM8711BL
MASTER CLOCK TIMING
t
XTIL
MCLK
t
XTIH
t
XTIY
Production Data
Figure 1 System Clock Timing Requirements
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T
A
= +25
o
C, Slave Mode fs = 48kHz, MCLK = 256fs
CLKDIV2=0 unless otherwise stated.
PARAMETER
System Clock Timing Information
MCLK System clock pulse width
high
MCLK System clock pulse width
low
MCLK System clock cycle time
MCLK Duty cycle
t
XTIH
t
XTIL
t
XTIY
18
18
54
40:60
60:40
ns
ns
ns
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
DIGITAL AUDIO INTERFACE – MASTER MODE
Figure 2 Digital Audio Data Timing - Master Mode
Test Conditions
AVDD, HPVDD, DVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, T
A
= +25
o
C, Slave Mode, fs = 48kHz, XTI/MCLK =
256fs unless otherwise stated.
PARAMETER
DACLRC propagation delay
from BCLK falling edge
DACDAT setup time to
BCLCK rising edge
DACDAT hold time from
BCLK rising edge
SYMBOL
t
DL
t
DST
t
DHT
TEST CONDITIONS
MIN
0
10
10
TYP
MAX
10
UNIT
ns
ns
ns
Audio Data Input Timing Information
w
PD, Rev 4.1, April 2007
10
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
