WM8711BL
Production Data
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK rising edge to CSB rising
edge
tSCS
60
ns
SCLK pulse cycle time
SCLK pulse width low
SCLK pulse width high
SDIN to SCLK set-up time
SCLK to SDIN hold time
CSB pulse width low
tSCY
tSCL
tSCH
tDSU
tDHO
tCSL
tCSH
tCSS
80
20
20
20
20
20
20
20
ns
ns
ns
ns
ns
ns
ns
ns
CSB pulse width high
CSB rising to SCLK rising
t3
t3
t5
SDIN
t4
t6
t2
t8
SCLK
t7
t1
t10
Figure 5 Program Register Input Timing – 2-Wire MPU Interface Timing
Test Conditions
AVDD, HPVDD, DBVDD = 3.3V, AGND = 0V, DCVDD = 1.5V, DGND = 0V, TA = +25oC, Slave Mode, fs = 48kHz, MCLK = 256fs
unless otherwise stated.
PARAMETER
SYMBOL
TEST CONDITIONS
MIN
TYP
MAX
UNIT
Program Register Input Information
SCLK Frequency
0
526
kHz
us
ns
ns
ns
ns
ns
ns
ns
ns
SCLK Low Pulsewidth
SCLK High Pulsewidth
Hold Time (Start Condition)
Setup Time (Start Condition)
Data Setup Time
t1
t2
1.3
600
600
600
100
t3
t4
t5
SDIN, SCLK Rise Time
SDIN, SCLK Fall Time
Setup Time (Stop Condition)
Data Hold Time
t6
300
300
t7
t8
600
t10
900
PD, Rev 4.1, April 2007
12
w
WOLFSON [ WOLFSON MICROELECTRONICS PLC ]
