X24022
Page Write
The X24022 is capable of an four byte page write
operation. It is initiated in the same manner as the byte
write operation, but instead of terminating the write cycle
after the first data word is transferred, the master can
transmit up to three more words. After the receipt of each
word, the X24022 will respond with an acknowledge.
After the receipt of each word, the two low order address
bits are internally incremented by one. The high order
five bits of the address remain constant. If the master
should transmit more than four words prior to generating
the stop condition, the address counter will “roll over”
and the previously written data will be overwritten. As
with the byte write operation, all inputs are disabled until
completion of the internal write cycle. Refer to Figure 6
for the address, acknowledge and data transfer
sequence.
Acknowledge Polling
The disabling of the inputs, during the internal write
operation, can be used to take advantage of the typical
5 ms write cycle time. Once the stop condition is issued
to indicate the end of the host’s write operation the
X24022 initiates the internal write cycle. ACK polling can
be initiated immediately. This involves issuing the start
condition followed by the slave address for a write
operation. If the X24022 is still busy with the write
operation no ACK will be returned. If the X24022 has
completed the write operation an ACK will be returned
and the master can then proceed with the next read or
write operation (See Flow 1).
Flow 1. ACK Polling Sequence
WRITE OPERATION
COMPLETED
ENTER ACK POLLING
ISSUE
START
ISSUE SLAVE
ADDRESS AND R/W = 0
ISSUE STOP
ACK
RETURNED?
YES
NEXT
OPERATION
A WRITE?
YES
NO
NO
ISSUE BYTE
ADDRESS
ISSUE STOP
PROCEED
PROCEED
3848 FHD F11
Figure 6. Page Write
S
T
BUS ACTIVITY:
A
R
MASTER
T
SDA LINE
BUS ACTIVITY:
X24022
S
A
C
K
A
C
K
A
C
K
A
C
K
A
C
K
S
T
O
P
P
SLAVE
ADDRESS
WORD
ADDRESS (n)
DATA n
DATA n+1
DATA n+3
NOTE: In this example n = xxxx 0000(B); x = 1 or 0
3848 FHD F12
6
XICOR [ XICOR INC. ]
