X25043/45
PIN CONFIGURATION
PIN DESCRIPTIONS
Serial Output (SO)
X25043/45
8-LEAD DIP/SOIC
SO is a push/pull serial data output pin. During a read
cycle, data is shifted out on this pin. Data is clocked out
by the falling edge of the serial clock.
CS
SO
WP
1
2
3
4
8
7
6
5
V
CC
RESET/RESET
Serial Input (SI)
SCK
SI
SI is the serial data input pin. All opcodes, byte ad-
dresses, and data to be written to the memory are input
onthispin. Dataislatchedbytherisingedgeoftheserial
clock.
V
SS
X25043/45
14-LEAD TSSOP
Serial Clock (SCK)
14
1
CS
SO
NC
NC
NC
WP
V
The Serial Clock controls the serial bus timing for data
input and output. Opcodes, addresses, or data present
on the SI pin is latched on the rising edge of the clock
input, while data on the SO pin changes after the falling
edge of the clock input.
CC
13
2
RESET/RESET
12
3
NC
NC
NC
SCK
SI
11
4
10
5
9
8
6
7
Chip Select (CS)
V
SS
When CS is HIGH, the X25043/45 is deselected and the
SO output pin is at high impedance and, unless an
internal write operation is underway, the X25043/45 will
be in the standby power mode. CS LOW enables the
X25043/45,placingitintheactivepowermode.Itshould
be noted that after power-up, a HIGH to LOW transition
on CS is required prior to the start of any operation.
3844 ILL F02.3
PIN NAMES
Symbol
CS
SO
Description
Chip Select Input
Serial Output
Serial Input
Write Protect (WP)
When WP is LOW, nonvolatile writes to the X25043/45
are disabled, but the part otherwise functions normally.
WhenWPisheldHIGH, allfunctions, includingnonvola-
tile writes operate normally. WP going LOW while CS is
still LOW will interrupt a write to the X25043/45. If the
internal write cycle has already been initiated, WP going
LOW will have no affect on a write.
SI
SCK
WP
VSS
VCC
Serial Clock Input
Write Protect Input
Ground
Supply Voltage
Reset Output
RESET/RESET
3844 PGM T01.1
Reset (RESET, RESET)
X25043/45, RESET/RESET is an active LOW/HIGH,
open drain output which goes active whenever VCC
falls below the mimimum VCC sense level. It will remain
active until VCC rises above the minimum VCC sense
level for 200ms. RESET/RESET also goes active if
the Watchdog timer is enabled and CS remains either
HIGH or LOW longer than the Watchdog time-out
period. Afallingedgeof CS willresetthewatchdogtimer.
2
XICOR [ XICOR INC. ]
