X28C256
CE Controlled Write Cycle
t
WC
ADDRESS
t
t
AH
AS
t
CW
CE
t
OES
OE
t
OEH
t
t
CH
CS
WE
t
DV
DATA IN
DATA VALID
t
t
DH
DS
HIGH Z
DATA OUT
3855 FHD F07
Page Write Cycle
OE(10)
CE
t
t
BLC
WP
WE
t
WPH
ADDRESS* (11)
I/O
LAST BYTE
BYTE 0
BYTE 1
BYTE 2
BYTE n
BYTE n+1
BYTE n+2
t
WC
*For each successive write within the page write operation, A –A should be the same or
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6
writes to an unknown address could occur.
3855 FHD F08
Notes: (10) Between successive byte writes within a page write operation, OE can be strobed LOW: e.g. this can be done with CE and WE
HIGH to fetch data from another memory device within the system for the next write; or with WE HIGH and CE LOW effectively
performing a polling operation.
(11) The timings shown above are unique to page write operations. Individual byte load operations within the page write must
conform to either the CE or WE controlled write cycle timing.
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XICOR [ XICOR INC. ]
