X28C64
PIN DESCRIPTIONS
Addresses (A
0
–A
12
)
The Address inputs select an 8-bit memory location
during a read or write operation.
Chip Enable (CE)
The Chip Enable input must be LOW to enable all read/
write operations. When
CE
is HIGH, power consumption
is reduced.
Output Enable (OE)
The Output Enable input controls the data output buffers
and is used to initiate read operations.
PIN NAMES
Symbol
A
0
–A
12
I/O
0
–I/O
7
WE
CE
OE
V
CC
V
SS
NC
FUNCTIONAL DIAGRAM
65,536-BIT
E2PROM
ARRAY
I/O1
I/O2
I/O3
I/O5
I/O6
12
13
15
17
18
I/O0
A0
11
10
VSS
I/O4
I/O7
14
16
19
CE
20
X28C64
OE
22
A10
21
A11
23
A8
25
NC
26
Data In/Data Out (I/O
0
–I/O
7
)
Data is written to or read from the X28C64 through the
I/O pins.
Write Enable (WE)
The Write Enable input controls the writing of data to the
X28C64.
PIN CONFIGURATION
PGA
Description
Address Inputs
Data Input/Output
Write Enable
Chip Enable
Output Enable
+5V
Ground
No Connect
3853 PGM T01
9
A1
A3
A5
8
A2
A4
A12
7
6
5
2
VCC
A9
28
24
NC
1
WE
27
4
A6
3
A7
BOTTOM VIEW
3853 FHD F04
X BUFFERS
LATCHES AND
DECODER
A0–A12
ADDRESS
INPUTS
Y BUFFERS
LATCHES AND
DECODER
I/O BUFFERS
AND LATCHES
I/O0–I/O7
DATA INPUTS/OUTPUTS
CE
OE
WE
VCC
VSS
3853 FHD F01
CONTROL
LOGIC AND
TIMING
2
XICOR [ XICOR INC. ]
