R
Virtex-II 1.5V Field-Programmable Gate Arrays
Architecture
Virtex-II Array Overview
Virtex-II devices are user-programmable gate arrays with various configurable elements. The Virtex-II architecture is
optimized for high-density and high-performance logic designs. As shown in
Figure 1,
the programmable device is
comprised of input/output blocks (IOBs) and internal configurable logic blocks (CLBs).
DCM
Global Clock Mux
DCM
IOB
Configurable Logic
Programmable I/Os
CLB
Block SelectRAM
Multiplier
DS031_28_100900
Figure 1:
Virtex-II Architecture Overview
Programmable I/O blocks provide the interface between
package pins and the internal configurable logic. Most
popular and leading-edge I/O standards are supported by
the programmable IOBs.
The internal configurable logic includes four major elements
organized in a regular array.
•
Configurable Logic Blocks (CLBs) provide functional
elements for combinatorial and synchronous logic,
including basic storage elements. BUFTs (3-state
buffers) associated with each CLB element drive
dedicated segmentable horizontal routing resources.
Block SelectRAM memory modules provide large
18-Kbit storage elements of True Dual-Port RAM.
Multiplier blocks are 18-bit x 18-bit dedicated
multipliers.
DCM (Digital Clock Manager) blocks provide
self-calibrating, fully digital solutions for clock
distribution delay compensation, clock multiplication
and division, coarse and fine-grained clock phase
shifting.
All programmable elements, including the routing
resources, are controlled by values stored in static memory
cells. These values are loaded in the memory cells during
configuration and can be reloaded to change the functions
of the programmable elements.
Virtex-II Features
This section briefly describes Virtex-II features.
Input/Output Blocks (IOBs)
IOBs are programmable and can be categorized as follows:
•
•
Input block with an optional single-data-rate or
double-data-rate (DDR) register
Output block with an optional single-data-rate or DDR
register, and an optional 3-state buffer, to be driven
directly or through a single or DDR register
Bi-directional block (any combination of input and
output configurations)
•
•
•
•
These registers are either edge-triggered D-type flip-flops
or level-sensitive latches.
IOBs support the following single-ended I/O standards:
•
•
•
•
LVTTL, LVCMOS (3.3 V, 2.5 V, 1.8 V, and 1.5 V)
PCI-X at 133 MHz, PCI (3.3 V at 33 MHz and 66 MHz)
GTL and GTLP
HSTL (Class I, II, III, and IV)
A new generation of programmable routing resources called
Active Interconnect Technology interconnects all of these
elements. The general routing matrix (GRM) is an array of
routing switches. Each programmable element is tied to a
switch matrix, allowing multiple connections to the general
routing matrix. The overall programmable interconnection is
hierarchical and designed to support high-speed designs.
DS031-1 (v1.7) October 2, 2001
Advance Product Specification
1-800-255-7778
Module 1 of 4
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