R
Spartan-3 FPGA Family: Pinout Descriptions
Detailed mechanical drawings for each package type are
available from the Xilinx website at the specified location in
Table 13.
Table 13: Xilinx Package Mechanical Drawings
Package
Web Link (URL)
http://www.xilinx.com/bvdocs/packages/vq100.pdf
http://www.xilinx.com/bvdocs/packages/tq144.pdf
http://www.xilinx.com/bvdocs/packages/pq208.pdf
http://www.xilinx.com/bvdocs/packages/ft256.pdf
http://www.xilinx.com/bvdocs/packages/fg320.pdf
http://www.xilinx.com/bvdocs/packages/fg456.pdf
http://www.xilinx.com/bvdocs/packages/fg676.pdf
http://www.xilinx.com/bvdocs/packages/fg900.pdf
http://www.xilinx.com/bvdocs/packages/fg1156.pdf
VQ100 / VQG100
TQ144 / TQG144
PQ208 / PQG208
FT256 / FTG256
FG320 / FGG320
FG456 / FGG456
FG676 / FGG676
FG900 /FGG900
FG1156 / FGG1156
Each package has three separate voltage supply
inputs—VCCINT, VCCAUX, and VCCO—and a common
ground return, GND. The numbers of pins dedicated to
these functions varies by package, as shown in Table 14.
A majority of package pins are user-defined I/O pins. How-
ever, the numbers and characteristics of these I/O depends
on the device type and the package in which it is available,
as shown in Table 15. The table shows the maximum num-
ber of single-ended I/O pins available, assuming that all
I/O-, DUAL-, DCI-, VREF-, and GCLK-type pins are used as
general-purpose I/O. Likewise, the table shows the maxi-
mum number of differential pin-pairs available on the pack-
age. Finally, the table shows how the total maximum user
I/Os are distributed by pin type, including the number of
unconnected—i.e., N.C.—pins on the device.
Table 14: Power and Ground Supply Pins by Package
Package
VQ100
TQ144
PQ208
FT256
VCCINT
VCCAUX
VCCO
8
GND
10
4
4
4
4
12
16
4
8
12
28
8
8
24
32
FG320
FG456
FG676
FG900
FG1156
12
12
20
32
40
8
28
40
8
40
52
16
24
32
64
76
80
120
184
104
22
www.xilinx.com
1-800-255-7778
DS099-4 (v1.5) July 13, 2004
Product Specification
XILINX [ XILINX, INC ]
