R
Spartan-3 FPGA Family: Pinout Descriptions
Table 16: VQ100 Package Pinout
Table 16: VQ100 Package Pinout
XC3S50
XC3S200
Pin Name
XC3S50
XC3S200
Pin Name
VQ100 Pin
Number
VQ100 Pin
Number
Bank
7
Type
VCCO
GND
Bank
Type
VCCINT
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
CONFIG
JTAG
VCCO_7
P6
N/A
VCCINT
P93
P52
P51
P98
P25
P24
P26
P99
P77
P100
P76
P78
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
N/A
GND
P3
VCCAUX CCLK
VCCAUX DONE
GND
P10
P20
P29
P41
P56
P66
P73
P82
P95
P7
GND
GND
GND
VCCAUX HSWAP_EN
VCCAUX M0
GND
GND
GND
GND
VCCAUX M1
GND
GND
VCCAUX M2
GND
GND
VCCAUX PROG_B
VCCAUX TCK
VCCAUX TDI
GND
GND
GND
GND
JTAG
GND
GND
VCCAUX TDO
VCCAUX TMS
JTAG
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
VCCAUX
VCCAUX
VCCAUX
VCCAUX
VCCINT
VCCINT
VCCINT
JTAG
P33
P58
P84
P18
P45
P69
User I/Os by Bank
Table 17 indicates how the available user-I/O pins are dis-
tributed between the eight I/O banks on the VQ100 pack-
age.
Table 17: User I/Os Per Bank in VQ100 Package
All Possible I/O Pins by Type
Maximum
Package Edge
I/O Bank
I/O
I/O
1
DUAL
DCI
2
VREF
GCLK
0
1
2
3
4
5
6
7
6
0
0
0
0
6
6
0
0
1
1
1
1
0
0
2
1
2
2
0
0
2
2
0
0
Top
7
2
2
8
5
2
Right
Bottom
Left
8
5
2
10
8
0
2
0
0
8
4
2
8
5
2
DS099-4 (v1.5) July 13, 2004
Product Specification
www.xilinx.com
1-800-255-7778
25
XILINX [ XILINX, INC ]
