Spartan-3 FPGA Family: DC and Switching Characteristics
R
PROG_B
(Input)
INIT_B
(Open-Drain)
T
SMCSCC
CS_B
(Input)
T
SMCCW
RDWR_B
(Input)
T
CCH
CCLK
(Input/Output)
T
SMDCC
D0 - D7
(Inputs)
T
SMCCD
1/F
CCPAR
T
CCL
T
SMWCC
T
SMCCCS
Byte 0
Byte 1
T
SMCKBY
Byte n
T
SMCKBY
Byte n+1
BUSY
(Output)
High-Z
BUSY
High-Z
DS099-3_05_041103
Notes:
1. Switching RDWR_B High or Low while holding CS_B Low asynchronously aborts configuration.
Figure 7:
Waveforms for Master and Slave Parallel Configuration
Table 36:
Timing for the Master and Slave Parallel Configuration Modes
All Speed Grades
Symbol
Clock-to-Output Times
Description
The time from the rising transition on the CCLK pin to a
signal transition at the BUSY pin
The time from the setup of data at the D0-D7 pins to the
rising transition at the CCLK pin
The time from the setup of a logic level at the CS_B pin to
the rising transition at the CCLK pin
The time from the setup of a logic level at the RDWR_B pin
to the rising transition at the CCLK pin
Slave/Master
Slave
Min
-
Max
12.0
Units
ns
T
SMCKBY
Setup Times
T
SMDCC
T
SMCSCC
T
SMCCW(2)
Both
10.0
10.0
10.0
-
-
-
ns
ns
ns
36
1-800-255-7778
DS099-3 (v1.3) March 4, 2004
Advance Product Specification
XILINX [ XILINX, INC ]
